Yeah, but that is initial power up from no power, and that works alright fo= r you. What does the __FPOR specify? Is that the 1024 clock delay before it= fires up the processor core to allow the internal voltages to settle? If s= o that may be sufficient delay, but that won't happen on activation of /MCL= R. I am thinking that when you operate the reset switch the rise time on /MCLR= is not fast enough - IIRC there is a minimum rise time specified so the pi= n doesn't stay in the linear region, although I haven't looked up the data = sheet for this particular chip but have seen this spec on other PIC data sh= eets. However you seemed to be talking of 47nF and 6k8, which I would have = thought would be fine - but again I haven't checked the data sheet. >=20 > > It may be that when powering up the board the internal brownout > > circuitry is holding things reset long enough for the /MCLR pin to get > > to a high enough voltage for this permutation not to be affected >=20 > Haven't tried a different RC yet, but did look at the config >=20 > Originally >=20 > config __FPOR,FPWRT_PWR1 ;no brown-out reset >=20 > Changed to >=20 > config __FPOR,FPWRT_PWR32 ;32ms >=20 > then >=20 > config __FPOR,FPWRT_PWR128 ;128ms >=20 > Same result. 128ms is way more than the /MCLR rise time >=20 > Joe >=20 >=20 > ----- > No virus found in this message. > Checked by AVG - www.avg.com > Version: 2015.0.5863 / Virus Database: 4328/9490 - Release Date: 04/08/15 >=20 > -- > http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive > View/change your membership options at > http://mailman.mit.edu/mailman/listinfo/piclist --=20 http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .