Hi - tx I forgot the tag.

Unfortunately not... for external input, FOSC<2:0> is 010.  See that=20
table in 6.1.  For all modes not 100 (i.e. not from internal=20
oscillator), you can either enable the PLL or not (the PLLEN or SPLLEN=20
column).  If you enable the PLL, then that 16Mhz becomes 64Mhz and goes=20
to Fosc @ 64Mhz, because PLLMUX is 00.  You can't control PLLMUX.

So... doesn't work.

At this point I'm going to do the xtal module @ 8Mhz approach and hope=20
that the signal is clean enough going to 6 pcbs stacked about 2 inches=20
apart to all work.  I may be able to use pcb#1's internal osc and CLKOUT=20
to generate the clock.

I started out with a FPGA based design, wow, really regret not doing it=20
that way.

J


IVP wrote:
> [tag added]
>
> Fig 16-1 in the datasheet seems to imply that a 4xPLL could
> be used on a 16MHz EC input to get 64MHz. I don't think
> it says you can't
>
> http://ww1.microchip.com/downloads/en/DeviceDoc/41675A.pdf
>
> If you can, then all processors could be clocked by one crystal
> module
>
> Joe
>
>
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