Other comments read and being thought about

> And a different observation; in the failure case you are raising
> CS, then a delay before DI and CLK rise.  The delay is about
> the size of a clock period

Time from CS =3D 1 to DI =3D 1 is 100us. That is, the delay between
CS raised and the first write of 0xFF to the SPI module

Time from DI =3D 1 to first clock L-H is 140ns. Clock period is 90ns

> Try changing your dsPIC code to raise DI and CLK at the same
> time as CS.

Yes, I can try that. The past couple of posts concerns a simple
routine that can be twiddled with. It does at the moment include
a deliberate 100us delay. When the circuit is running properly the
next routine would issue the CMD0. As the card is currently in the
fault condition and fails in a few seconds to a few minutes, it
hopefully will not be too time-consuming to see what, if anything,
has an effect

> e.g. are you handling a time consuming interrupt at this point;
> perhaps you could mask interrupts?

Interrupts (TMR1) are off - actually not needed - whilst comms to
the card/file are being established. The timer is used to extract data
from the buffer RAM and deliver it to the DAC at the required audio
sample rate

Joe

PS congratulations on winning the Cricket World Cup. OK, NZ
hasn't even finished batting yet but, c'mon, 167-7 ?


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