On 19/03/15 13:56, Nathan House wrote:
> Good morning!
>
> I'm a student working on a directed research project involving a PCB desi=
gn
> for a PIC18 microcontroller.
>
> None of my professors have much PCB design experience, so I don't have
> anyone I can go to for feedback on the schematic or layout. I know you're
> all professionals and are busy with your own work, but if anyone has a fe=
w
> free minutes and would like to critique my board layout I would really
> appreciate your advice.
>   =20
Be aware that altium's standard pin header footprints are designed for=20
PCB facilities that work on finished hole size (most proffesional PCB=20
vendors do). If the facility you use work on drill size (our in-house=20
facility does, I think olimex does too) then the holes are too small to=20
easilly fit the headers (I've had to resort to a hammer in the past).

Not sure why you have put capacitors on PGC and PGD, i'm sure the=20
instructions for the ICD2 said explicitly NOT to fit such capacitors.

You have silkscreen over a VIA, this may make it hard to read and may=20
annoy some board vendors.

You have no capacitor on the input side of the regulator. This seems=20
pretty unusual (though I notice that the regulator vendor doesn't=20
specify one).

High speed signal integrity won't be great. If the pinout of the headers=20
is not set in stone then it may be better to put the ground pins in the=20
midddle (or even add more of them) and try to keep the loop area between=20
signal traces and their ground return paths as small as possible.

Even if the pinout is fixed it looks like some carefully placed extra=20
VIAs and/or some slight movement of tracks could dramatically reduce the=20
length of the ground path from the left hand ground pin back to the=20
processor.

The IO speeds on a PIC are not massive so it will almost certainly work=20
as designed but paying attention to the loop area of return paths for=20
any signals with fast edges and minimising it wherever practical is a=20
good habbit to get in to. Especially if you ever get into designing=20
anything that needs to be EMC tested.

QFNs are a PITA to solder (yes I know there are youtube videos that make=20
it look easy but those guys have had a LOT of pracice). yes it can be=20
done but it's certainly not something I'd reccomend putting on your=20
first board (and yes it's annoying that the 28 pin PICs only come in=20
annoyingly large dil or wide SOIC packages or annoyingly tiny QFNs).
--=20
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