Chetan Let see the problem as it should be seen. The PIC microcontroller becomes an aggressor for the rest of the signals you may have, assuming your design is a mixed one (it has also analog and/or RF on the same board). To choose correctly the number of decoupling caps and their values you need to know which are the frequencies you have to suppress. The simplest way to compute those without using a sniffer, a spectrum analyzer and the first revision of your PCB is to think at the Xtal frequency (and the PLL if it's active) and it's odd harmonics up to 3. As long you are using reversed geometry decoupling caps (with lowest ESR and inductance) the number of decoupling caps can decrease dramatically. See the theory on the manufacturers site like here: http://www.avx.com/docs/catalogs/licc.pdf The best practice rule is to keep the capacitors on the same layer as the chip is, to avoid vias between the micro pin and decoupling caps. However for a BGA (DSP, FPGA) this is impossible. How I would do? I'll put one small cap (10nF, 47nF, 100nF or so, as required) very close (3-5mm if possible) from every power pin of the TQFP, on the same layer as PICmicro is. The rest of the bigger caps can then be stuffed a little bit far away, on the same or on the opposite side of the PCB. Vasile On Sun, Sep 2, 2012 at 9:30 AM, Chetan Bhargava wrote= : > My original question was about practical designs. How many of you > manage to put 4x de-caps on 4x set of power pins of a TQFP > microcontroller (PIC)? > I managed to put 3x caps (1x on same layer with PIC and 2x on bottom > layer with vias). Would this be close to best practices? > > Thanks > > Chetan Bhargava > http://microz.blogspot.com > > > On Sat, Sep 1, 2012 at 10:40 PM, Chetan Bhargava > wrote: > > My design is a power controller that delivers ~10x power rails to a > > high speed serial memory IC. The serial PHY is 10GHz Ser-Des and the > > ripple tolerances are pretty low (10mv p-p max). This chip works with > > Altera and Xilinx FPGAs hence similar design considerations. > > > > I can very well understand the coupling requirements. > > > > Thanks > > > > Chetan Bhargava > > http://microz.blogspot.com > > > > > > On Sat, Sep 1, 2012 at 10:23 PM, Harold Hallikainen > > wrote: > >> I've generally put them "as close as possible" and had no problems. Bu= t, > >> that's not very specific. > >> > >> I did some analysis on bypass capacitors for a couple Altera FPGAs. Th= ey > >> have a nice spreadsheet that takes a LOT into consideration. It takes > the > >> ripple current on the pin and the allowed ripple voltage, then > determines > >> the maximum impedance allowed. It then looks at the impedance of the > >> capacitor, the impedance of traces to the capacitors, impedance of via= s, > >> parallel capacity of power planes, and internal bypassing for very hig= h > >> frequencies. It's very thorough. But, I haven't seen anything like tha= t > >> for a PIC. > >> > >> Harold > -- > http://www.piclist.com PIC/SX FAQ & list archive > View/change your membership options at > http://mailman.mit.edu/mailman/listinfo/piclist > --=20 http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .