Hi all,

I'm writing the computed branch below for an 18F. The s/w
reads a 4-bit DIP switch on PortC <3:0> and branches to one
of 16 flag-setting routines. Each of these is 4 instructions x two
cycles long, hence the * 8. So far so good

The code crosses from 0x01FE to 0x0200 in the middle of
routine mode04

The branch reaches mode04 OK, but PCLATH is still 0x01
when code tries to branch to mode05, which starts at 0x0202,
and so program flow jumps back to 0x0102. Writing to PCL
does not overflow into PCLATH

Can I make PCLATH advance to 0x02 if (W + PCL) > FE
under any circumstances (ie wherever code happens to be)

For example, if I execute

         movff   pcl,temp0  ;eg PCL =3D 0xD8

         addwf   temp0  ;result of W * 8
         skpnc
         incf    pclath

after the rlncf's, it seems to work. But seems a bit inelegant and
might not work as code is moved/edited

I have plenty of code space and can org the mode routines to just
after a boundary so that they all have a common PCLATH but
that seems a bit crude. Or org the computed branch as a subroutine
after the main code (as you might for a table etc) rather than
embedding it in-line

TIA

Joe

mode     clrf    flags4        ;clear all mode settings
         clrf    flags5
         clrf    flags6

         movlw   high(mode00)
         movwf   pclath

         movfw   portc         ;read DIP switch
         andlw   0x0f          ;keep bits 0,1,2,3
         clrc
         rlncf   wreg          ;W * 8
         rlncf   wreg
         rlncf   wreg
         addwf   pcl

mode00   bsf     flags4,
         bsf     flags4,
         bcf     flags4,
         bra     clk_loop

mode01   bsf     flags4,
         bra     clk_loop
         nop
         nop

mode02   bsf     flags4,
         bcf     flags5,
         bra     clk_loop
         nop
..
..
..

mode15   bsf     flags6,
         nop
         nop
         nop

clk_loop


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