Beware this calculation is at 25deg C, and the question of "how hot will=20
it get?" is not straightforward to answer.

Look up "temperature rise in FETs" from december 22 2014 for a thread=20
about it.

In my use - highspeed PWM for LED drivers, I'm doing a design at this=20
very moment to get 2600 steps at 24Khz - the switching speed wasn't the=20
problem.  (I'm using a gate driver FWIW.)  100% is the worst case for=20
heat, driving the gate at 9V.

Also Josh - camera flicker is going to depend on the camera and the=20
settings, how much other light there is, and the power supplies used.  I=20
sell a 32-channel DMX dimmer designed to have no flicker on camera, and=20
the rates required has varied from customer to customer.  1800 Hz has=20
been fine (Metropolitan opera in NYC making a DVD of a performance), and=20
other times 7.2Khz was needed (a variety of movies and TV studios).  You=20
will also possibly have to contend with audible noise from your circuit=20
or the power supply when switching significant current in the audible range=
..

Hence the 24Khz in the latest new design.

If you'd rather buy than build drop me a line for details.

J


IVP wrote:
>> Is there a way to calculate how much power I will be dissipating in
>> the FET package? I'm trying to figure out how much of a heatsink I
>> might potentially need.
>
> I'm not familiar with the linear characteristics of FET (ie how resistanc=
e
> changes as it turns on/off) but I'm willing to find out with you
>
> https://www.fairchildsemi.com/datasheets/FQ/FQP13N06L.pdf
>
> The FQP13N06L d/s says Ron is 110mR @ Vgs =3D 5V, so that means
> the minimum wattage in the package at 8A and 100% duty cycle will be
>
> P =3D I*I*R =3D 64 x 0.11 =3D 7.04W
>
> Package power dissipation @ 25C per d/s is 45W (seems a lot for a
> TO-220), so it would seem that if the FET is turned on hard (no PWM)
> it doesn't need a heatsink. IME that appears true as I've run large DC
> motors with FETs and they get only a little warm when driven properly,
> maybe a watt or two.
>
> So, the question is, during the period when the gate goes from 0V to
> 5V, and back, how does the resistance vary between drain and source ?
> It will obviously flip between very high and 110mR during the gate time
>
> I know that the object is to get current into/out of the gate capacitance
> to charge/discharge it, and the time taken to do that can be worked
> out from the current source/sink available and the capacitor value.
>
> Ideally the d/s would have an R vs Vgs graph, but perhaps something
> can be inferred from Figure 2
>
> If Vgs =3D 2V, then Id =3D 0.2A. At 24V drain-source, that suggests that
>
> Rds =3D 24/0.2 =3D 120 ohms
>
> P =3D I*I*R in that situation would be 4.8W
>
> And so on, through the rise/fall time of the PWM edge. Maybe it's that
> simple, it's probably not though.
>
> I'm sure there's an equation for it
>
> Joe
>
>
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