http://ww1.microchip.com/downloads/en/DeviceDoc/30487c.pdf Section 15.10 last paragraph. Delay is caused by need to synchronise the external interrupt to the internal clock On 5 January 2015 at 21:24, Nicola Perotto wrote: > > On 05/01/2015 18:25, David C Brown wrote: > > On mid range PICs interrupt latency is "three or four instruction cycle= s" > > which meets the criteria of "within several instruction times" rather > > neatly. > > Uhm... this is interesting. Can you point to some documentations? > Thanks > N > * > * > -- > http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive > View/change your membership options at > http://mailman.mit.edu/mailman/listinfo/piclist > --=20 __________________________________________ David C Brown 43 Bings Road Whaley Bridge High Peak Phone: 01663 733236 Derbyshire eMail: dcb.home@gmail.com SK23 7ND web: www.bings-knowle.co.uk/dcb --=20 http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .