Easy - Pick a random mid-range PIC. I picked a PIC16F883. Download the
datasheet. Look at Figure 14-8. It says interrupt latency is 3-4 Tcy and
provides a nice diagram showing the details. You can see the dummy cycles
inserted as the processor cancels and restarts the instruction pipeline.

That is for a very specific piece of hardware. The more general answer,
which I provided earlier, is a somewhat larger range depending on the
processor architecture. It should still fit into the "several" instruction
cycle range for almost any processor. No matter how complex the architectur=
e
gets, the designer usually wants to minimize interrupt latency so some of
the stuff will happen in parallel. Some very simplistic processors might ge=
t
it done in one cycle, but that would be a rarity and still fits within the
answer..

-----Original Message-----
From: piclist-bounces@mit.edu [mailto:piclist-bounces@mit.edu] On Behalf Of
Nicola Perotto
Sent: Monday, January 05, 2015 2:25 PM
To: Microcontroller discussion list - Public.
Subject: Re: [EE] Need help writing questions for exam


On 05/01/2015 18:25, David C Brown wrote:
> On mid range PICs interrupt latency is "three or four instruction cycles"
> which meets the criteria of "within several instruction times" rather=20
> neatly.

Uhm... this is interesting. Can you point to some documentations?
Thanks
         N
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