On mid range PICs interrupt latency is "three or four instruction cycles"
which meets the criteria of "within several instruction times" rather
neatly.

>
> On most chips a) is definitely wrong: an interupt is handled after
> *each* instruction. You can of course argue that "within several
> instruction times" is included within "after each instruction", but I
> would consider that argumentative.
>
> Wouter
>
> >
> > BillW
> >
> >
>
> --
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