On most chips a) is definitely wrong: an interupt is handled after *each* instruction. You can of course argue that "within several instructio= n times" is included within "after each instruction", but I would consider that argumentative. I disagree. I think A is the correct answer for several reasons.=20 First, we do need to make some assumptions. That indicates a problem with the question. What does "responded to" mean? To me it means "How long is it until the first instruction of the interrupt code is executed?" It could also be interpreted from the application's point of view in terms of something like when the timer interrupt occurs, how long is it until the pi= n that is changed in the interrupt routine actually changes value? Another general assumption is that the microprocessor does not support prioritized interrupts. If it does, a low-priority interrupt could be delayed for a significant amount of time (at least 10s to 100s of instructions cycles) while higher priority interrupts are processed. B and C are wrong simply because you do not know the CPU clock speed so any answer in terms of an actual time cannot be correct. It is common for microcontroller clocks to run between 30KHz or less (power saving modes) an= d 100MHz (a currently fast processor), but even 4GHz might be considered vali= d for a current microprocessor (i.e. a PC), but maybe not a microcontroller. That range of clock speeds would reasonably put the interrupt service time in the range of nanoseconds to milliseconds. An understanding of the range of clock speeds commonly in use would invalidate B and C as answers. D is not correct because interrupts do not wait for the CPU to not be busy. The whole concept is to do something right-now and interrupt whatever it is busy doing. A is correct under my assumption that we are talking about the delay until the first interrupt instruction is executed in most CPU architectures. The CPU must wait until the current instruction (which could be a multi-cycle instruction) is executed. That is usually 0-2 instruction cycles. If it is executing an interruptible instruction, it must wait until the instruction reaches a point where it can be interrupted and have its status saved. That's probably 0-4 cycles. Usually the instruction processing pipeline mus= t be flushed and re-loaded. That is at least 1-4 cycles. There may be further delays due to context switching and hardware status saving and flushing and re-loading of other low-level caches. Overall, something in the order of 2-10 instruction cycles would elapse between the interrupt flag being set and the first instruction of the interrupt being executed, so I think "several instruction periods" is a good answer for most CPU architectures. --=20 http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .