Alan, You ask some very good questions. I think if you look carefully at the datasheets for most FETs, the conditions where they specify Vgs are almost all quasi-static (far longer than the typical turn-on time of the FET, which is roughly 100ns), so that inductive effects are non-existent. The resistance of the source lead(s) is small enough that resistive effects can be neglected, too, in most cases, so they are able to skirt the issue of where exactly they are measuring Vgs. However, I think the real answer is at the die itself. Certainly, in terms of turn on/ turn off behavior, the source lead inductance can play a very major role, as you imply. It also can play a big role in balancing current among several paralleled FETs. Some of the newer packages really help in this department, such as the 7-lead D2PAK (has four source pins, one gate pin, the one trimmed drain pin, and then the drain pad, for a total of seven leads) and a similar package from Infineon which is flatter. I have been experimenting with using these multiple source pins as a pseudo Kelvin connection. So far, my results have been promising - I have a prototype brushless motor drive which can do 100 Amps RMS all day long and 200 Amps RMS for 10 second bursts, at up to 60V DC bus, using three paralleled Infineon FETs in each leg. It's designed for sinusoidal current control so the effective line-line RMS voltage is 42V, This works out to 7kW continuous, 14kW for 10 seconds. Gate drive ICs usually have rail-to-rail outputs whose output resistance rises sharply as you get near the rails - similar to a CMOS logic gate or rail-to-rail op-amp. So, 10V in to a driver chip would be 10V out, but it might take, say, 10 microseconds for it to finish charging the gate to within 0.1V of 10V. The critereon for a FET being fully on is that the gate is at least one Vgs threshold voltage above BOTH the source AND the drain. For low to medium current, this is usually trivially satisfied by being able to drive Vgs to a comfortable margin above Vgs_thresh, but at high drain current, you need to get Vgd > 0 in order to get Vds below a volt or two, so that's when it is important to have the few extra volts above the maximum Vgs_threshold to keep the turn_on transition time short. There are plots in all decent FET datasheets I've seen, showing Rds_ON for various Vgs and Vds values, at various temperatures. I am wondering if the original poster is having some kind of parasitic oscillation problem so that his FETs are not turning full ON and staying ON., Sean On Tue, Dec 23, 2014 at 4:44 AM, wrote: > My other question is where do the manufacturers who spec the chip measure > the Vgs? Is it at the die, or at the end of the outside leads? Is voltage > drop across the source lead out of the chip dropping enough to 'ground > bounce' the source pad? With a chip quoted as giving such a low Rdson one > would hope not. > > But also what do you get in terms of chip heating if you drive it with a > proper 10V instead of 'around 9V to the driver chip'? How much gate drive > is being lost in the driver not going to the rails? > > I don't have any experience driving power FETs myself (but have a couple > of projects I want to do with motors), but do recall warnings given here = in > the past over how much Rdson changes with 'near enough' drive voltages. > > > > -- > http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive > View/change your membership options at > http://mailman.mit.edu/mailman/listinfo/piclist > --=20 http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .