One more item - the series inductor really needs to be a type which will be lossy at the frequencies encountered in ESD (1MHz to 1GHz), so it will almost certainly be a ferrite bead with one or a small number of turns. If you tried to use an air core inductor, it might resonate with the capacitor and fail to dissipate the energy until the TVS clamped. On Fri, Nov 28, 2014 at 12:33 PM, Sean Breheny wrote: > Hi Jason, > > Your latest schematic is getting closer to something that would work well= .. > I have a few suggestions: > > 1) SMD resistors do not act like true resistors at the voltages > encountered in ESD. Very often the ESD pulse will jump right across an 08= 05 > resistor as if it were not there at all. > 2) Even worse than #1, thin film SMD resistors (the typical SMD type) can > be damaged by ESD, changing their value permanently. > 3) The best strategy that I know of is to use a small inductor or ferrite > bead in series with the incoming signal, followed by a capacitor to GND a= nd > a TVS diode to GND. In such a scheme, it is important that the GND layout > prevent the return current from the cap and TVS from going through an > uncontrolled path in the main ground plane, since it can cause ground > bounce large enough to damage or at least disrupt other parts of the > circuit. I like to use a separate "ESD GND" as a ring around the edge of > the PCB. I tie this ring to the main GND plane at only one point and all > I/O ESD protection devices connect to the ESD GND and all external GND > connections also go only to the ESD GND. If there is a metal chassis, it > ties to ESD GND. The inductor slows the rise time of the ESD pulse and > dissipates some of its energy/drops some of its voltage. The cap absorbs > most of the rest of the charge and the TVS clamps the peak voltage to > something safe for the logic to follow. > > I must note that my strategy #3 has only partially been tested. In other > words, I have designed it into devices which have stood up well to ESD bu= t > I haven't done a side-by-side test where I built a board with my strategy > and one with a different one and compared protection levels. > > Sean > > > On Fri, Nov 28, 2014 at 10:34 AM, Jason White < > whitewaterssoftwareinfo@gmail.com> wrote: > >> Thanks Vasile, I read a few app notes and made some changes. >> >> Heres what I have so far (see attached). I added a zener along with >> several capacitors to help shunt the ESD discharge. I also attempted >> to model the pulse and parasitics in the attached LTSPICE file. I'm >> not sure if its terribly accurate, it is showing to transients of +-1v >> at the base of the transistor using the machine [ESD] model. >> >> >> >> >> >> -- >> Jason White >> >> -- >> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive >> View/change your membership options at >> http://mailman.mit.edu/mailman/listinfo/piclist >> >> > --=20 http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .