I've decided to switch my FPGA design work from regular verilog to=20
systemverilog. The main motivation for this is the greater range of=20
types available for passing arround signals making things less verbose=20
and easier to parameterise.

When I'm working with a new language (or even one i've used for a while=20
but don't use all the time) I like to have a book on hand to check=20
little details in. Does anyone have any suggestions on what if any books=20
are good for systemverilog RTL stuff (not especially interested in the=20
verification stuff at this point).

--=20
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