I was mistaken, it seems that the simulator simply copy the interrupt's
priority level to the fields CSS and EICSS of register SRSCtl for any
interrupt.

According to the documentation, it should copy the field corresponding
to the interrupt level from register PRISS (or perhaps SRSMap or
SRSMAP2, it is unclear). I set these registers to all zeros, so in
theory the selected shadow register set would be set zero (the original
register set) for all interrupts.


Isaac


On 09/10/2014 21:58, Isaac Marino Bavaresco wrote:
> What happened toMicrochip's support? I tried to open a ticket with the
> technical support but it appears that now there is only "Comunity
> Support" (forum).
>
>
> Below is a copy of the question I posted in the forum. Any ideas?
>
>
> Best regards,
>
> Isaac
>
>
>> I'm porting my RTOS from PIC32MX to PIC32MZ and i'm experiencing weird
>> problems in the MPLAB-X simulator.
>> =20
>> Currently I'm using no shadow register sets, but when the Timer2
>> interrupt service routine begins the shadow set 1 is automatically
>> selected.
>> =20
>> I have:
>> =20
>> PRISS =3D 0x00000000
>> SRSMAP =3D 0x00000000
>> SRSMAP2 =3D 0x00000000
>> =20
>> Before the interrupt triggers, SRSCtl =3D 0x1C000000 but at the ISR
>> entrance, SRSCtl =3D 0x1C040001.
>> =20
>> That's weird because all the other interrupts behave correctly.
>> =20
>> TIMER1 and TIMER2 have interrupt priority =3D 1 (T1IP =3D 1, T1IS =3D 0,
>> T2IP =3D 1, T2IS =3D 0)
>> UART2 has interrupt priority =3D 2 (U2RXIP =3D 2, U2RXIS =3D 0, U2TXIP =
=3D 2,
>> U2TXIS =3D 0)
>> =20
>> Both Timer1 and Timer2 share the exact same priority, then I would
>> expect both to use the same shadow register set (in this case, the
>> original set). Timer1 uses the original set but Timer2 unexpectedly is
>> using shadow set 1. UART2 has a different priority and also uses the
>> correct set.
>> =20
>> I hope this is a bug in the simulator, because things will be much
>> harder if this bug occurs when debugging the real hardware.
>> =20
>> Does anybody have any hint? Am I missing some configuration? Can
>> anybody confirm that this is a bug in the simulator?
>> =20
>> =20
>> Best regards,
>> =20
>> Isaac
>
>



--=20
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