Hmmm... actually it's currently set to PORT (ie: PORTDbits.RD0, etc).  I=20
should change that.

Cheers,
-Neil.


On 8/27/2014 4:46 PM, Jan-Erik Soderholm wrote:
> Just a thought...
>
>   > Technically, both bits cannot even change at the same time,
>   > as they're being individually set (ie: I'm not setting the
>   > PORT or LAT in one cycle).
>
> When setting the port pins, are you using PORTx or LATx ?
>
> Jan-Erik.
>
>
>
> Neil wrote 2014-08-27 20:36:
>> Having some issues when I run a PIC18F46K22 at higher speeds.  I'm
>> bit-banging I2C (as both EUSARTs are in use for serial comms), and the
>> code works as expected at low speeds.  When I go to higher speeds
>> (32Mhz) the bit timings for the stop condition are odd, and I comms with
>> a serial-EEPROM fails.  Anyone know why?
>>
>> (1) This works -- 8Mhz, no PLL...
>> http://veisystems.com/stuff/2014-08-27-PIC-HS-Issue-01-8Mhz-GOOD.gif
>>
>> You'll see that there's 5.5us between the positive edge of SCL to the
>> positive edge of SDA, as expected.  FWIW, I'm using some Nop()'s to get
>> the correct timing.
>>
>> (2) This is the same section of the bit pattern (the I2C stop
>> condition), for which I only changed the PLLCFG fuse to ON.  This fails.=
...
>> http://veisystems.com/stuff/2014-08-27-PIC-HS-Issue-02-32Mhz%28PLL%29-FA=
IL.gif
>>
>> Technically, both bits cannot even change at the same time, as they're
>> being individually set (ie: I'm not setting the PORT or LAT in one
>> cycle).  My logic analyzer is sampling at 24Mhz here, so it can
>> certainly catch the timing.  Also, the low pulse in this screenshot is
>> also way off in timing, compared to the previous (working) test.
>>
>> (3) Without recompiling or reflashing (to ensure that there's no
>> different optimization going on), I just changed the 8Mhz crystal to
>> 4Mhz so it's running at 16Mhz now (with the PLL on).  This works again..=
..
>> http://veisystems.com/stuff/2014-08-27-PIC-HS-Issue-03-16Mhz%28PLL%29-GO=
OD.gif
>>
>> I also checked the code size between (1) and (2) where the PLL was
>> enabled, and code size is the same, so there's no different optimization
>> going on.  I'm not sure what to do from here.  I do need this chip to
>> run at a higher Fosc (48Mhz).  Any thoughts?
>>
>> Cheers,
>> -Neil.
>>

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