Having some issues when I run a PIC18F46K22 at higher speeds.  I'm=20
bit-banging I2C (as both EUSARTs are in use for serial comms), and the=20
code works as expected at low speeds.  When I go to higher speeds=20
(32Mhz) the bit timings for the stop condition are odd, and I comms with=20
a serial-EEPROM fails.  Anyone know why?

(1) This works -- 8Mhz, no PLL...
http://veisystems.com/stuff/2014-08-27-PIC-HS-Issue-01-8Mhz-GOOD.gif

You'll see that there's 5.5us between the positive edge of SCL to the=20
positive edge of SDA, as expected.  FWIW, I'm using some Nop()'s to get=20
the correct timing.

(2) This is the same section of the bit pattern (the I2C stop=20
condition), for which I only changed the PLLCFG fuse to ON.  This fails...
http://veisystems.com/stuff/2014-08-27-PIC-HS-Issue-02-32Mhz%28PLL%29-FAIL.=
gif

Technically, both bits cannot even change at the same time, as they're=20
being individually set (ie: I'm not setting the PORT or LAT in one=20
cycle).  My logic analyzer is sampling at 24Mhz here, so it can=20
certainly catch the timing.  Also, the low pulse in this screenshot is=20
also way off in timing, compared to the previous (working) test.

(3) Without recompiling or reflashing (to ensure that there's no=20
different optimization going on), I just changed the 8Mhz crystal to=20
4Mhz so it's running at 16Mhz now (with the PLL on).  This works again...
http://veisystems.com/stuff/2014-08-27-PIC-HS-Issue-03-16Mhz%28PLL%29-GOOD.=
gif

I also checked the code size between (1) and (2) where the PLL was=20
enabled, and code size is the same, so there's no different optimization=20
going on.  I'm not sure what to do from here.  I do need this chip to=20
run at a higher Fosc (48Mhz).  Any thoughts?

Cheers,
-Neil.

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