--_002_2014082622542423abd49ekruskalhomecheadca_
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: quoted-printable

On Tue, 12 Aug 2014 15:19:52 +0000 (UTC)
Mike <mikerj@clara.net> wrote:

> Is it possible you are using the incorrect SPI mode (clock polarity
> and phase) and it's giving marginal timing that is failing
> occasionally?

Sorry for not replying earlier; I was away from home and not in
possession of regular Internet access. The manual explicitly states
that mode (0, 0) is the proper mode to use, as well as showing sample
timing diagrams that match up with that description, and that is what I
have both selected in my microcontroller code and also implemented in
VHDL.
--=20
Christopher Head

--_002_2014082622542423abd49ekruskalhomecheadca_
Content-Type: text/plain; name="ATT00001.txt"
Content-Description: ATT00001.txt
Content-Disposition: attachment; filename="ATT00001.txt"; size=224;
	creation-date="Wed, 27 Aug 2014 06:05:21 GMT";
	modification-date="Wed, 27 Aug 2014 06:05:21 GMT"
Content-Transfer-Encoding: base64

LS0gDQpodHRwOi8vd3d3LnBpY2xpc3QuY29tL3RlY2hyZWYvcGljbGlzdCBQSUMvU1ggRkFRICYg
bGlzdCBhcmNoaXZlDQpWaWV3L2NoYW5nZSB5b3VyIG1lbWJlcnNoaXAgb3B0aW9ucyBhdA0KaHR0
cDovL21haWxtYW4ubWl0LmVkdS9tYWlsbWFuL2xpc3RpbmZvL3BpY2xpc3QNCg==

--_002_2014082622542423abd49ekruskalhomecheadca_--
.