Without doing all the math, I think it is safe to assume that the App=20
note code is safe to use in the circuit specified, which has a 4 MHz=20
crystal.  The app note also says
>  If a faster clock is used,
> the code may need to be modified to ensure all timing
> specs are met.
You're gonna need some delays or interrupts to satisfy the Fclk spec=20
with a 64 MHz crystal (but you don't mention any prescaling) .  Assuming=20
your Fclk is in spec, it should always be safe to sample SDA on the=20
rising edge of SCL.
I would use the I2C timing specs more to decide on top level design than=20
to write the line to line code.  IOW, design it so that Fclk <=3D 400 kHz=20
and Tlow >=3D 1300 nS.

Joe W


On 08/13/2014 04:14 PM, Neil wrote:
> I'm bit-banging I2C to a 24LC16B serial EEPROM with a PIC18F46K22 and
> working out the best timing for running at 64Mhz Fosc.  When reading
> bits from the EEPROM, I'm confused if the time for the data on the
> EEPROM output to be valid from the SCL pulse is referenced from the
> positive clock edge, or the negative clock edge.
>
> Figure 1-1 and Table 1-2 in the serial-EEPROM datasheet (
> http://ww1.microchip.com/downloads/en/DeviceDoc/21703L.pdf ) shows that
> parameter 11 ("Output valid from clock", which seems to be the one I
> want) is measured from the negative edge of the SCL pulse, but
> Microchip's AN997 (for bit-banging I2C) has this code, which seems to be
> based off the positive clock pulse...
>
> void bit_in(unsigned char *data)
> {
>       SCL =3D 0;                        // Ensure SCL is low
>       SDA_TRIS =3D 1;                   // Configure SDA as an input
>       SCL =3D 1;                        // Bring SCL high to begin transf=
er
>       *data &=3D 0xFE;                  // Assume next bit is low
>       if (SDA)                        // Check if SDA is high
>       {
>           *data |=3D 0x01;              // If high, set next bit
>       }
>       SCL =3D 0;                        // Bring SCL low again
> } // end bit_in(unsigned char *data)
>
> You'll see above that the clock is sent high, data read in, then the
> clock pulse is completed by sending it low.  So which is correct?
>
> Alternately, if the data at the serial-EEPROM output does not change
> (which I suspect, but am not sure about) after the clock pulse goes low,
> I guess I could just play it safe and wait the 900ns after that, though
> that would be unnecessarily wasting cycles which I could be using to do
> other processing.
>
> Cheers,
> -Neil.
>
>


--=20
Joe Wronski
Stillwater Embedded Engineering
www.stillwatereng.net

--=20
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