I'm bit-banging I2C to a 24LC16B serial EEPROM with a PIC18F46K22 and=20
working out the best timing for running at 64Mhz Fosc.  When reading=20
bits from the EEPROM, I'm confused if the time for the data on the=20
EEPROM output to be valid from the SCL pulse is referenced from the=20
positive clock edge, or the negative clock edge.

Figure 1-1 and Table 1-2 in the serial-EEPROM datasheet (=20
http://ww1.microchip.com/downloads/en/DeviceDoc/21703L.pdf ) shows that=20
parameter 11 ("Output valid from clock", which seems to be the one I=20
want) is measured from the negative edge of the SCL pulse, but=20
Microchip's AN997 (for bit-banging I2C) has this code, which seems to be=20
based off the positive clock pulse...

void bit_in(unsigned char *data)
{
     SCL =3D 0;                        // Ensure SCL is low
     SDA_TRIS =3D 1;                   // Configure SDA as an input
     SCL =3D 1;                        // Bring SCL high to begin transfer
     *data &=3D 0xFE;                  // Assume next bit is low
     if (SDA)                        // Check if SDA is high
     {
         *data |=3D 0x01;              // If high, set next bit
     }
     SCL =3D 0;                        // Bring SCL low again
} // end bit_in(unsigned char *data)

You'll see above that the clock is sent high, data read in, then the=20
clock pulse is completed by sending it low.  So which is correct?

Alternately, if the data at the serial-EEPROM output does not change=20
(which I suspect, but am not sure about) after the clock pulse goes low,=20
I guess I could just play it safe and wait the 900ns after that, though=20
that would be unnecessarily wasting cycles which I could be using to do=20
other processing.

Cheers,
-Neil.


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