Can you lower the SPI clock substantially and see if you get the same behav= ior? /Ruben > On Sat, 09 Aug 2014 01:06:14 +0200 > "Ruben J=F6nsson" wrote: >=20 > > Are you saying that the FCS is wrong when this happens but when you > > read the buffer a second time the data (and FCS) is right? >=20 > That is exactly what I am saying. I can detect that the problem has > happened because the FCS comes out wrong, and I can work around the > problem (with, presumably, 1/65,536 probability of false accept) by > reading the receive buffer over and over until the FCS comes out right. >=20 > > It could also be a problem with the part that writes the > > (long-)address for the register that you should read from the RX-FIFO > > so you are actually reading at the wrong address. This doesn't > > explain the wrong FCS though. >=20 > I thought so, except that I am seeing exactly the same problem on two > completely different hosts receiving frames (one an STM32F4 MCU using > its hardware SPI peripheral driven by C code, and the other an FPGA on > which I wrote VHDL from the ground up to do SPI and everything above > it), and also I captured one of the bad bytes on a scope and everything > on MOSI (including the address) looked right to me. > --=20 > Christopher Head >=20 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D Ruben J=F6nsson AB Liros Electronic Box 9124, 200 39 Malm=F6, Sweden TEL INT +46 40142078 FAX INT +46 40947388 ruben@pp.sbbs.se =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D --=20 http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .