Redux: PIC10F322 datasheet 40001585B.pdf pp. 60 "Modifying Flash Memory": I=
t
is sort of described there, but are there notes/discussion on endurance?
Permitted repeat counts etc?

Searching for "endurance" in said PDF yields:

pp 165: Cell endurance: min. 10kE/W cycles. That is per cell or per row? It
says per call, and per cell is not so good imo. If it is per row, 10K sound=
s
a lot until one runs some numbers. Assume a maximum of 10 writes average pe=
r
day, probably to the same row without wear levelling, one gets a
statistically probable failure before 3 years of operation, assuming the
part holds up according to the untested parameter (per ds). Normal external
SPI or I2C "High" endurance EEPROM is rated at 1 million cycles per cell or
more now and I think 10 million cycles are possible without wear levelling.

pp. 99 mentions "High Endurance Flash" locations but underneath a note says
"High Endurance Flash applies to low byte of each address in range". Which
is beyond confusing, to me. So a low byte is a part of a 16 word/byte row
but only the low byte is high endurance? And the ds 10kE/W parameter (above=
,
pp 165) does not mention if it refers to High Endurance or otherwise.

Any more data snippets on this thorny subject? I am trying to put the
picture together...

Digging further, searching for "High Endurance Flash" on Microchip.com:

TB072 91072a.pdf "FLASH Memory Technology: Considerations for Application
Design" is a fresh breeze from 2003. Its content does not apply directly to
10F322 issues but I can't find anything more relevant?

-- Peter


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