Also connect the powersupply traces (VDD and GND) to the capacitor instead =
of=20
the chip. To keep impedance between the cip and the capacitor lower than=20
between the chip and powersupply.

I usually try to keep one side of the board as a groundplane as solid as=20
possible and then place the capacitor as close as the VDD pin as possible.=
=20
Powersupply VDD is routed to one side of the capacitor VDD pad and the chip=
 VDD=20
is routed to the other side of the VDD pad (a Y connection). In cases where=
 VDD=20
and VSS is close together in the chip, the same is done with the VSS connec=
tion=20
(not connecting the VSS pin of the chip directly to the groundplane but to =
the=20
VSS pad of the capacitor). The VSS pad of the capacitor is connected to the=
=20
ground plane with several vias if possible.

/Ruben


> Em 25/05/2014 18:05, Harold Hallikainen escreveu:
> > I suspect it makes no difference in the situation you described. Each
> > trace will have inductance, so we end up with a series L-C-L. If the tw=
o
> > Ls add up to the same inductance, it does not matter which is where, si=
nce
> > they are in series. But, you can reduce the inductance by keeping the
> > traces as short as possible and as wide as possible.
>=20
>=20
> In such situations (single- or double-sided boards) I try to create a
> very low inductance/resistance ground network, sometimes sacrificing the
> VCC network's inductance/resistance (thinner and longer tracks) and
> connecting the decoupling capacitors to ground at well located positions
> and to VCC the closest to the IC pins as possible. This way, I reduce
> the ground bounce and the capacitors compensate for the poor VCC tracks.
>=20
> It is important to remember that the ground network is the voltage
> reference in a board and that if it has too much inductance and/or
> resistance, some nodes can develop voltage differences under high
> current conditions (caused by resistance) or fast transients (caused by
> inductance). These voltage differences between ground nodes can make an
> IC misinterpret a signal sent by another IC.
>=20
> Some logic families (TTL specially) have much higher noise margin for
> the logic level high than for logic level low, so it is a good idea to
> keep the ground network as strong as possible (sometimes I add jumpers
> to strengthen it).
>=20
> For double-sided boards I try to shape the bottom layer as close to a
> ground plane as possible, routing most of the tracks on the top layer.
> If a ground plane is not possible, one good solution is to elect a
> ground node as the "central-ground" and radiating wide tracks from it to
> the several peripheral sub-circuits. Even better if the central node can
> be shaped as a large uninterrupted copper area.
>=20
> Isaac
>=20

--=20
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