Martin K wrote:
> I want to divide an RF signal down from 100 MHz to something between 1 an=
d
> 5 MHz for precise counting. The RF is essentially CW with a bit of freque=
ncy
> modulation. Signal power is -5 to -25 dBm which corresponds to a voltage =
on
> a 50 ohm load of 12.5mV to 125mV.
>
> My plan is to use a very high speed comparator to capture the (AC coupled=
)
> zero crossing and put the output (LVPECL) into a couple 1:8 dividers in
> series. The signal will probably end up going to an FPGA so LVDS or LVCMO=
S
> is desirable.

What kind of FPGA are you using that can't handle the 100 MHz directly?
Most modern FPGAs can handle serial I/O in the multi-GHz range, and even
the general-purpose I/O and logic will run at hundreds of MHz.

-- Dave Tweed
--=20
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
.