Indeed, the slightly larger PIC is a good idea, but there are certain advantages of using an external serial to parallel interface: a) The main board can be made very small and use a four to six pin connector instead of a 16 pin one. b) If the LCD is not used in all the units, you can save some money. c) The serial to parallel interface can be used for other peripherals if necessary d) You have already the smaller PIC. e) It uses less wire to connect the LCD to the main board. One of the disadvantages it that the interface is much slower. Isaac Em 28/04/2014 18:10, David C Brown escreveu: > Why use a low pin count PIC with extra chips and discrete when a slightly > larger PIC would be cheaper and simpler? > On 28 Apr 2014 14:43, "Isaac Marino Bavaresco" > wrote: > >> Em 28/04/2014 09:36, Larry Bradley escreveu: >>> An LCD display connected to a PIC requires a minimum of 6 port pins. >>> With small pin-count PICs, this can be a problem. >>> >>> Many years ago, when the Basic Stamp came out, some clever chap provide= d >>> a serial LCD display - it used RS232 - to reduce the pin count (this wa= s >>> in the days of the 16F84). >>> >>> I want to do the same thing but using SPI. (I just want it for myself - >>> I don't plan on producing anything). I can always get a chip with SPI >>> hardware to use as the LCD driver, but I though I would try it with a >>> couple of chips I have on hand, using software SPI. >>> >>> I've done SPI master in software - no problem. It seems to me that doin= g >>> the slave shouldn't be difficult at all - it is really a very simple >>> system. I've search the Internet to see if there are any software slave >>> implementations out there, but no luck. Rather than re-invent the wheel= , >>> do any of you know of any? >> >> The attached circuit (PDF) shows how to implement an SPI-like slave (it >> works with an SPI master) with a 74HT/HCT595 that uses just two pins of >> the PIC. >> >> The trick is that while SCK is clocking, the parallel load input is kept >> at logic level zero by the transistor and RC constant (R4*C2). As soon >> the pin SCK stops clocking (inactive state =3D logic level zero), the >> capacitor starts charging until the parallel load pin sees a logic level >> one and transfers the contents of the shift-register to the outputs. >> If you are worried about the slow rising signal at the parallel load >> input, a single-gate Schmitt-Trigger gate can be used to square the sign= al. >> >> Several 74HC595 can be chained to expand the output pins to any multiple >> of 8. >> >> >> Isaac >> >> >> -- >> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive >> View/change your membership options at >> http://mailman.mit.edu/mailman/listinfo/piclist >> >> --=20 http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .