Hi All, I have a design that needs a little tweak that I'm not sure how=20
to best do.  Or even what it is called.

I have a design were there is a highspeed comparator that compares the=20
voltage drop across a current sense resistor with a reference voltage,=20
and thus it produces a "current too low" / "current too high" signal=20
that is used to tell a buck dc/dc chip to "pump" or "not pump".

This is working ... in almost all cases.  There are some combinations of=20
target current, dc/dc input voltage, and dimming (this is a very=20
highspeed PWM constant current driver) whereby I get flicker, which is=20
happening because the dc/dc chip is getting a highspeed barrage of=20
"pump" vs. "not pump" on its feedback input pin (the aforementioned=20
comparator output signal with some additional tweaks on it.)  This is=20
causing it to reset itself, it looks like, although from the datasheet I=20
don't see why it would be a problem, but I'm using it somewhat=20
unconventionally.

What I would like to do is have that comparator output be conditioned to=20
have a minimum on or off time.  So if the output is low, then goes high=20
no matter how briefly, the dc/dc feedback ("FB") gets a high of minimum=20
of (say) 5usec.  After 5usec, if the comparator output has gone low, the=20
FB gets a low again with a minimum of (say) 5usec (it would be nice to=20
have the option to make the minimum times different for high vs. low).=20
However, on the other hand, if after that 5usec high time, the=20
comparator output is still high, the FB pin continues to get a high, but=20
the instant the comparator output goes low, the FB pin goes low with the=20
5usec minimum time.

In other words, I'd rather not have a circuit that merely samples the=20
comparator at 5usec intervals and sends that to the FB pin.

Still with me?

The design has 7 channels like this, however only two of them are high=20
current (700 & 800mA vs. 150mA), and only those two ever have this=20
flicker problem.

This could be done in firmware of course, some kind of as fast as=20
possible read of the comparator and a bit of code to implement a delay,=20
but the PIC running it all is already running external PWM hardware and=20
serial input and so I'd rather not add this to the mix.  And unless it=20
is done as interrupts that trigger on either edge I could of course miss=20
fast low-high-low transitions that happen between sampling times.

I was looking around for some kind of clever circuit using a 555 type=20
scheme but haven't found anything close enough to be adapted.

A scheme involving a CPLD or a tiny as possible FPGA with a highspeed=20
clock or some external RC delay timer would work.

Another approach would be to use a slower comparator or slow down the=20
rise/fall time of the current sense resistor's voltage at the comparator=20
input.  Doing this means I can't regulate the current when the PWM=20
on-time is very short, which is already not as good as I'd like.

Yet another approach might be to add some hysteresis to the comparator's=20
reference voltage, however that isn't convenient to do to the design=20
as-is (and 44 pcbs have been made) so while it could fix it for the next=20
spin, something that can be patched into the current spin is preferred.

Part of the problem is that I'm not sure what this kind of thing is=20
called.  It seems like it should be relatively common, at least in an=20
earlier age before microcontrollers totally took over the world.  (not a=20
bad thing, but there is less need for crafty little standalone circuits=20
like this these days).

Any thoughts appreciated!
J
--=20
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