Byron Jeff wrote 2014-02-10 17:55:
> On Mon, Feb 10, 2014 at 03:48:23PM +0000, alan.b.pearce@stfc.ac.uk wrote:
>>>> What I'm trying to do is generate a data stream for the 2811 variety o=
f
>>>> RGB pixels.  This is while receiving a DMX stream using interrupts.
>>>> David...
>>>
>>> I'm not familar with that PIC - some SPI ports always leave a gap, thou=
gh this
>>> can sometimes depend whether you're using the "buffer not full" or
>>> "transfer complete" to reload.
>>
>
>> I would have thought the SPI system would always leave a gap because of
>> the framing pulse that identifies the start and finish of a byte (word)
>> of data. DMA is not going to help that situation.
>
> SPI on the 16F1933 isn't framed, so I don't think that's it.
>
> There's a much simpler explanation for the gap. On the PIC 16F1933 the
> SSPBUF register is half duplex. The outgoing byte is written and the
> incoming byte is read from the same register. The rub is that the incomin=
g
> byte cannot be ignored. In order to keep sync each incoming byte must be
> read after the transmission of the outgoing byte. This has to be done eve=
n
> if the incoming byte is junk...

 From the 1933 datasheet, chap 24.2.4.1 :

"...Setting the BOEN bit of the SSPCON3 register will enable writes
to the SSPBUF register, even if the previous byte has not been read."


> So the delay in reading the incoming byte,
> clearing teh buffer, writing the outgoing byte, and starting to shift it
> can easily cause a gap between two outgoing bytes.

Now, from earlier posts I got the impression that the root
problem was not the MSSP module itself, but timing problems
between serving the MSSP module and the DMX interface
services by the same PIC.

Jan-Erik.


>
> BAJ
>
>>
>>
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