On 12/24/2013 9:55 AM, Dwayne Reid wrote:
> At 08:23 AM 12/24/2013, Jason White wrote:
>>> I've been asked if I can conjure up  a device that will allow 6 increme=
ntal
>>> rotary encoders and 10 ADC inputs.
>> Two ideas
>> 1) If large IO is a concern I would be tempted to use a small CPLD to
>> route the encoders to the MCU (make them addressable like a RAM), and
>> then perhaps give it some logic to generate an interrupt on change for
>> the processor.
> The above is sort of what I suggested - but a CPLD could, I think,
> potentially be a better solution than a PIC.  The advantage of a CPLD
> is that the inputs could be self-clocking and implementing the full
> state-machine decoder (times 6) within the CPLD is trivial.
>
> The interface to the host processor would be similar to using another
> small PIC, except that using I2C might be easier on the CPLD than
> with a PIC.  SPI is similar in both cases.
>
> But two different options to accomplish the same task.
>
> The real bonus of off-loading the encoder tasks to a separate device
> is that the host is now much less busy because it doesn't have to
> deal with the rotary encoders.  This can be a very worthwhile tradeoff.
>
> dwayne
>
BUT the advantage of the PIC would be that you could advance the=20
counters INSIDE the PIC, offloading the entire task.

--Bob

--=20

The only place success comes before work is in the dictionary.

VINCE LOMBARDI

--=20
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