At 08:23 AM 12/24/2013, Jason White wrote: > > I've been asked if I can conjure up a device that will allow 6 increme= ntal > > rotary encoders and 10 ADC inputs. > >Two ideas >1) If large IO is a concern I would be tempted to use a small CPLD to >route the encoders to the MCU (make them addressable like a RAM), and >then perhaps give it some logic to generate an interrupt on change for >the processor. The above is sort of what I suggested - but a CPLD could, I think,=20 potentially be a better solution than a PIC. The advantage of a CPLD=20 is that the inputs could be self-clocking and implementing the full=20 state-machine decoder (times 6) within the CPLD is trivial. The interface to the host processor would be similar to using another=20 small PIC, except that using I2C might be easier on the CPLD than=20 with a PIC. SPI is similar in both cases. But two different options to accomplish the same task. The real bonus of off-loading the encoder tasks to a separate device=20 is that the host is now much less busy because it doesn't have to=20 deal with the rotary encoders. This can be a very worthwhile tradeoff. dwayne --=20 Dwayne Reid Trinity Electronics Systems Ltd Edmonton, AB, CANADA (780) 489-3199 voice (780) 487-6397 fax www.trinity-electronics.com Custom Electronics Design and Manufacturing --=20 http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .