Sorry - some shorthand that I didn't explain. You may not like some of my shortcuts . DDR is a carryover from when I was writing code for Motorola 68xx family. It is a much more familiar term to most people than "tris", which is Microchip-specific. DDR is, of course, Data Direction Register. I didn't point out that _bljmpr & _bhjmpr are flag bits in a byte of RAM and that _blrolo & _blrohi are the PIC pins that have both the relay drivers (digital transistors) *and* the configuration jumpers (with isolation resistors). When the PIC pin is set to output, it drives the transistor. When the PIC pin is set to input, the combination of pull-up resistor, isolation resistor, and driver base resistors are chosen to guarantee a reliable logic-LO or logic-HI when reading the configuration jumper. The PIC pin has TTL level thresholds, which makes it easy. If you look carefully at the memory map for a 12-bit-core or 14-bit-core PIC, you will see that the TRIS registers map to exactly the same RAM address as the pins themselves, except that the TRIS registers are in RAM Page 1 and the port registers are in RAM Page 0. Thus the macros "rampg0" and "rampg1" - these manipulate the RP0 & RP1 bits in the status register. It is so very convenient that the same pin label can be used for manipulating both the DDR bit as well as the actual PIC pin, depending upon how the RAM page bits are set. So: the program enters the routine knowing that the PIC pins _blrolo & _blrohi are set to be output and LO. First: go to RAM page 1 and set those PIC pins to i/p, back to RAM page 0, pre-clear the flag bits _bljmpr & _bhjmpr, then test the level on each of the PIC pins and set the flag bits HI if the logic level on the corresponding PIC pin is high. Finally, return the PIC pins back to being output. A few things: I would normally pre-clear each flag bit just before it is tested. However, I gain an extra microsecond of settling time for free by grouping the pre-clear instructions together, before the pin tests. I do get a glitch on the relay coil(s) if the configuration jumper(s) is/are set for logic HI. However, that glitch is only about 8us and has absolutely NO effect on the relay. What prompted my original question was me wondering if the port output latches got changed from their original state if I *read* the port pin with a 'btfsc' instruction. Matt got me back on track. dwayne At 03:52 PM 12/7/2013, Jan-Erik Soderholm wrote: >A few minor notices... :-) > >"DDR", isn't that what an AVR calls the TRIS registers? > >Note that BCF/BSF are exactly the kind of instructions >where you need to be carefull *not* to get into an >R-M-W situation! In your original post you only wrote >about *reading* the I/O pins. > >Then I do not undetstand this : > > > bsf _BLROLO ;boiler o/p DDR bits become inputs > >Is _BLROLO a bit in a TRIS register? >If not, what is the comment realy saying? > >I think that we need the definitions of your >_Bxxxxx symbols also to understand the context. > >Jan-Erik. > > > >Dwayne Reid wrote 2013-12-07 21:31: > > Thanks for the reminder. > > > > I specifically look for and avoid the R-M-W > > issues that you mention - I got bit very early in > > my PIC programming career and learned from that. > > > > The real problem that caused me to bring this > > question to the PIClist group of gurus was that I > > simply had a "brain fart" and, for the life of > > me, couldn't get past this question. > > > > The kicker, of course, is that I've been doing > > exactly what I was questioning for literally > > decades now - with no problems. But it looked funny this time. > > > > I'm so very thankful that I have all of you to > > help get me back on the straight and narrow when I *do* go off the rail= s. > > > > For what its worth, this is the code that I was questioning: > > > > SmY1 ;ON period - restore pins to i/p, sample inputs > > ;first, read jumpers on boiler o/p pins > > rampg01 > > bsf _BLROLO ;boiler o/p DDR bits become inputs > > bsf _BLROHI > > rampg10 > > bcf _BLJMPR > > bcf _BHJMPR > > btfsc _BLROLO ;3us settling time should be plenty > > bsf _BLJMPR ;jumper on boiler LO o/p pin > > btfsc _BLROHI > > bsf _BHJMPR ;jumper on boiler HI o/p pin > > rampg01 > > bcf _BLROLO ;restore boiler o/p DDR bits back to = out > > bcf _BLROHI > > rampg10 > > > > ;now do stuff that keeps relays OFF (external > faults). Pins are still o/p & LO > > > > Boiler o/p pins were previously set to o/p & LO > > in a previous state upon entering the above > > routine. I wanted to make sure that they > > remained LO at the conclusion of the routine. > > > > Many thanks! > > > > dwayne > > > > > > At 04:07 PM 12/6/2013, Ruben J=F6nsson wrote: > >> What Matt says below is all correct. > However, when the bit is set as an input > >> and the pin is high (possibly by a pull up > resistor) if you do a bit operation > >> (bsf, bcf) on any other bits for that port (not latch bits if the PIC = has > >> separate latch registers), the outport latch > that you originally set low will > >> be changed to high. This is because the bit > operation instructions actually > >> reads the whole port, changes (or not) the > bit you requested and then writes > >> back the whole port. > >> > >> This is especially important to keep in mind if > >> you have a wired or setup where > >> several outputs on a bus actively drives the bus > >> only to a low state and lets a > >> pullup resistor pull the line high when no other > >> on the bus drives it low. This > >> can effectively be done by writing a 0 to > the output latch and then change the > >> output with the tris register (0=3Dpin actively > >> driven low, 1=3Dpassively pulled up > >> to high if no other is driving low). The outport > >> latch will then be set high if > >> you do a bsf/bcf on another bit in the port register (again, not the l= atch > >> register) when the tris bit is set to 1 for > the bus pin. In this situation it > >> is not enough to change the tris to 0 but you also have to change the = port > >> latch back to 0 before. > >> > >> /Ruben > >> > >> > >>> On Fri, 06 Dec 2013 13:00:36 -0700, Dwayne Reid wrote: > >>>> At 12:06 PM 12/6/2013, Matt Pobursky wrote: > >>>>> Dwayne, > >>>>> > >>>>> Since the output port bit and TRIS latches are separate registers, = you > >>>>> can toggle the TRIS bit all day long and not change the logic level= of > >>>>> the port bit. It will simply toggle the port bit from Hi-z (input) = to > >>>>> output at whatever level is set in the output port bit latch. > >>>>> > >>>>> You can only get into trouble with R-M-W when the port is read then > >>>>> written back to the port bit registers. > >>>>> > >>>> > >>>> You are close to what I am talking about but missed the mark just a = bit: > >>>> I set the pin to o/p, > >>> > >>> write 0 to TRIS register bit -- pin output > >> bit latch unaffected, output pin will > >>> actively drive whatever logic level it was before clearing TRIS bit > >>> > >>>> write that pin to being LO, > >>> > >>> write 0 to output latch bit, output will actively drive LOW > >>> > >>>> then turn the pin back to i/p and *read* a logic HI on the pin > >>> > >>> write 1 to TRIS register bit, output port > bit latch unaffected, output bit > >>> is still LOW, but output pin is Hi-z so reads whatever logic level is > >>> present at pin. > >>> > >>>> Question: what state is the pin output latch in now? > >>> > >>> Output latch is still 0 as reading the port or setting/clearing the T= RIS > >>> register does not affect the output latch > >>> > >>> Think about this -- if read port register > instructions affected the output > >>> bit latch states then all port reads would result in unpredictable po= rt > >>> operation. > >>> > >>> If you look at the block diagram of the PIC > >> IO port structure in any of the data > >>> sheets, you'll see that the only way an > >> output bit latch is changed is with a > >>> write operation. > >>> > >>> I've done this numerous times where I set the port bit low, set pin t= o > >>> output to discharge a capacitor, set pin back to input which allows a= the > >>> cap charge, read and wait for a logic 1 state (RC timing on one pin). > >>> Alternate discharging and timing by setting > >> or clearing the TRIS bit, never have > >>> to change the logic 0 on the port bit latch > >> as it's persistent. I suspect you > >>> are doing something very similar to this. > >>> > >>>> My recollection is that the pin is read in the quadrature clock phas= e Q1 > >>>> or Q2 and the pin latch is written in Q3 or Q4. > >>>> > >>>> dwayne > > > > >-- >http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive >View/change your membership options at >http://mailman.mit.edu/mailman/listinfo/piclist -- Dwayne Reid Trinity Electronics Systems Ltd Edmonton, AB, CANADA (780) 489-3199 voice (780) 487-6397 fax www.trinity-electronics.com Custom Electronics Design and Manufacturing -- http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .