A few minor notices... :-) "DDR", isn't that what an AVR calls the TRIS registers? Note that BCF/BSF are exactly the kind of instructions where you need to be carefull *not* to get into an R-M-W situation! In your original post you only wrote about *reading* the I/O pins. Then I do not undetstand this : > bsf _BLROLO ;boiler o/p DDR bits become inputs Is _BLROLO a bit in a TRIS register? If not, what is the comment realy saying? I think that we need the definitions of your _Bxxxxx symbols also to understand the context. Jan-Erik. Dwayne Reid wrote 2013-12-07 21:31: > Thanks for the reminder. > > I specifically look for and avoid the R-M-W > issues that you mention - I got bit very early in > my PIC programming career and learned from that. > > The real problem that caused me to bring this > question to the PIClist group of gurus was that I > simply had a "brain fart" and, for the life of > me, couldn't get past this question. > > The kicker, of course, is that I've been doing > exactly what I was questioning for literally > decades now - with no problems. But it looked funny this time. > > I'm so very thankful that I have all of you to > help get me back on the straight and narrow when I *do* go off the rails. > > For what its worth, this is the code that I was questioning: > > SmY1 ;ON period - restore pins to i/p, sample inputs > ;first, read jumpers on boiler o/p pins > rampg01 > bsf _BLROLO ;boiler o/p DDR bits become inputs > bsf _BLROHI > rampg10 > bcf _BLJMPR > bcf _BHJMPR > btfsc _BLROLO ;3us settling time should be plenty > bsf _BLJMPR ;jumper on boiler LO o/p pin > btfsc _BLROHI > bsf _BHJMPR ;jumper on boiler HI o/p pin > rampg01 > bcf _BLROLO ;restore boiler o/p DDR bits back to ou= t > bcf _BLROHI > rampg10 > > ;now do stuff that keeps relays OFF (external faults). Pins are still o/= p & LO > > Boiler o/p pins were previously set to o/p & LO > in a previous state upon entering the above > routine. I wanted to make sure that they > remained LO at the conclusion of the routine. > > Many thanks! > > dwayne > > > At 04:07 PM 12/6/2013, Ruben J=F6nsson wrote: >> What Matt says below is all correct. However, when the bit is set as an = input >> and the pin is high (possibly by a pull up resistor) if you do a bit ope= ration >> (bsf, bcf) on any other bits for that port (not latch bits if the PIC ha= s >> separate latch registers), the outport latch that you originally set low= will >> be changed to high. This is because the bit operation instructions actua= lly >> reads the whole port, changes (or not) the bit you requested and then wr= ites >> back the whole port. >> >> This is especially important to keep in mind if >> you have a wired or setup where >> several outputs on a bus actively drives the bus >> only to a low state and lets a >> pullup resistor pull the line high when no other >> on the bus drives it low. This >> can effectively be done by writing a 0 to the output latch and then chan= ge the >> output with the tris register (0=3Dpin actively >> driven low, 1=3Dpassively pulled up >> to high if no other is driving low). The outport >> latch will then be set high if >> you do a bsf/bcf on another bit in the port register (again, not the lat= ch >> register) when the tris bit is set to 1 for the bus pin. In this situati= on it >> is not enough to change the tris to 0 but you also have to change the po= rt >> latch back to 0 before. >> >> /Ruben >> >> >>> On Fri, 06 Dec 2013 13:00:36 -0700, Dwayne Reid wrote: >>>> At 12:06 PM 12/6/2013, Matt Pobursky wrote: >>>>> Dwayne, >>>>> >>>>> Since the output port bit and TRIS latches are separate registers, yo= u >>>>> can toggle the TRIS bit all day long and not change the logic level o= f >>>>> the port bit. It will simply toggle the port bit from Hi-z (input) to >>>>> output at whatever level is set in the output port bit latch. >>>>> >>>>> You can only get into trouble with R-M-W when the port is read then >>>>> written back to the port bit registers. >>>>> >>>> >>>> You are close to what I am talking about but missed the mark just a bi= t: >>>> I set the pin to o/p, >>> >>> write 0 to TRIS register bit -- pin output >> bit latch unaffected, output pin will >>> actively drive whatever logic level it was before clearing TRIS bit >>> >>>> write that pin to being LO, >>> >>> write 0 to output latch bit, output will actively drive LOW >>> >>>> then turn the pin back to i/p and *read* a logic HI on the pin >>> >>> write 1 to TRIS register bit, output port bit latch unaffected, output = bit >>> is still LOW, but output pin is Hi-z so reads whatever logic level is >>> present at pin. >>> >>>> Question: what state is the pin output latch in now? >>> >>> Output latch is still 0 as reading the port or setting/clearing the TRI= S >>> register does not affect the output latch >>> >>> Think about this -- if read port register instructions affected the out= put >>> bit latch states then all port reads would result in unpredictable port >>> operation. >>> >>> If you look at the block diagram of the PIC >> IO port structure in any of the data >>> sheets, you'll see that the only way an >> output bit latch is changed is with a >>> write operation. >>> >>> I've done this numerous times where I set the port bit low, set pin to >>> output to discharge a capacitor, set pin back to input which allows a t= he >>> cap charge, read and wait for a logic 1 state (RC timing on one pin). >>> Alternate discharging and timing by setting >> or clearing the TRIS bit, never have >>> to change the logic 0 on the port bit latch >> as it's persistent. I suspect you >>> are doing something very similar to this. >>> >>>> My recollection is that the pin is read in the quadrature clock phase = Q1 >>>> or Q2 and the pin latch is written in Q3 or Q4. >>>> >>>> dwayne > > --=20 http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .