Thanks for the reminder. I specifically look for and avoid the R-M-W=20 issues that you mention - I got bit very early in=20 my PIC programming career and learned from that. The real problem that caused me to bring this=20 question to the PIClist group of gurus was that I=20 simply had a "brain fart" and, for the life of=20 me, couldn't get past this question. The kicker, of course, is that I've been doing=20 exactly what I was questioning for literally=20 decades now - with no problems. But it looked funny this time. I'm so very thankful that I have all of you to=20 help get me back on the straight and narrow when I *do* go off the rails. For what its worth, this is the code that I was questioning: SmY1 ;ON period - restore pins to i/p, sample inputs ;first, read jumpers on boiler o/p pins rampg01 bsf _BLROLO ;boiler o/p DDR bits become inputs bsf _BLROHI rampg10 bcf _BLJMPR bcf _BHJMPR btfsc _BLROLO ;3us settling time should be plenty bsf _BLJMPR ;jumper on boiler LO o/p pin btfsc _BLROHI bsf _BHJMPR ;jumper on boiler HI o/p pin rampg01 bcf _BLROLO ;restore boiler o/p DDR bits back to out bcf _BLROHI rampg10 ;now do stuff that keeps relays OFF (external faults). Pins are still o/p = & LO Boiler o/p pins were previously set to o/p & LO=20 in a previous state upon entering the above=20 routine. I wanted to make sure that they=20 remained LO at the conclusion of the routine. Many thanks! dwayne At 04:07 PM 12/6/2013, Ruben J=F6nsson wrote: >What Matt says below is all correct. However, when the bit is set as an in= put >and the pin is high (possibly by a pull up resistor) if you do a bit opera= tion >(bsf, bcf) on any other bits for that port (not latch bits if the PIC has >separate latch registers), the outport latch that you originally set low w= ill >be changed to high. This is because the bit operation instructions actuall= y >reads the whole port, changes (or not) the bit you requested and then writ= es >back the whole port. > >This is especially important to keep in mind if=20 >you have a wired or setup where >several outputs on a bus actively drives the bus=20 >only to a low state and lets a >pullup resistor pull the line high when no other=20 >on the bus drives it low. This >can effectively be done by writing a 0 to the output latch and then change= the >output with the tris register (0=3Dpin actively=20 >driven low, 1=3Dpassively pulled up >to high if no other is driving low). The outport=20 >latch will then be set high if >you do a bsf/bcf on another bit in the port register (again, not the latch >register) when the tris bit is set to 1 for the bus pin. In this situation= it >is not enough to change the tris to 0 but you also have to change the port >latch back to 0 before. > >/Ruben > > > > On Fri, 06 Dec 2013 13:00:36 -0700, Dwayne Reid wrote: > > > At 12:06 PM 12/6/2013, Matt Pobursky wrote: > > >> Dwayne, > > >> > > >> Since the output port bit and TRIS latches are separate registers, y= ou > > >> can toggle the TRIS bit all day long and not change the logic level = of > > >> the port bit. It will simply toggle the port bit from Hi-z (input) t= o > > >> output at whatever level is set in the output port bit latch. > > >> > > >> You can only get into trouble with R-M-W when the port is read then > > >> written back to the port bit registers. > > >> > > > > > > You are close to what I am talking about but missed the mark just a b= it: > > > I set the pin to o/p, > > > > write 0 to TRIS register bit -- pin output=20 > bit latch unaffected, output pin will > > actively drive whatever logic level it was before clearing TRIS bit > > > > > write that pin to being LO, > > > > write 0 to output latch bit, output will actively drive LOW > > > > >then turn the pin back to i/p and *read* a logic HI on the pin > > > > write 1 to TRIS register bit, output port bit latch unaffected, output = bit > > is still LOW, but output pin is Hi-z so reads whatever logic level is > > present at pin. > > > > > Question: what state is the pin output latch in now? > > > > Output latch is still 0 as reading the port or setting/clearing the TRI= S > > register does not affect the output latch > > > > Think about this -- if read port register instructions affected the out= put > > bit latch states then all port reads would result in unpredictable port > > operation. > > > > If you look at the block diagram of the PIC=20 > IO port structure in any of the data > > sheets, you'll see that the only way an=20 > output bit latch is changed is with a > > write operation. > > > > I've done this numerous times where I set the port bit low, set pin to > > output to discharge a capacitor, set pin back to input which allows a t= he > > cap charge, read and wait for a logic 1 state (RC timing on one pin). > > Alternate discharging and timing by setting=20 > or clearing the TRIS bit, never have > > to change the logic 0 on the port bit latch=20 > as it's persistent. I suspect you > > are doing something very similar to this. > > > > > My recollection is that the pin is read in the quadrature clock phase= Q1 > > > or Q2 and the pin latch is written in Q3 or Q4. > > > > > > dwayne --=20 Dwayne Reid Trinity Electronics Systems Ltd Edmonton, AB, CANADA (780) 489-3199 voice (780) 487-6397 fax www.trinity-electronics.com Custom Electronics Design and Manufacturing --=20 http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .