What Matt says below is all correct. However, when the bit is set as an inp=
ut
and the pin is high (possibly by a pull up resistor) if you do a bit operat=
ion
(bsf, bcf) on any other bits for that port (not latch bits if the PIC has
separate latch registers), the outport latch that you originally set low wi=
ll
be changed to high. This is because the bit operation instructions actually
reads the whole port, changes (or not) the bit you requested and then write=
s
back the whole port.

This is especially important to keep in mind if you have a wired or setup w=
here
several outputs on a bus actively drives the bus only to a low state and le=
ts a
pullup resistor pull the line high when no other on the bus drives it low. =
This
can effectively be done by writing a 0 to the output latch and then change =
the
output with the tris register (0=3Dpin actively driven low, 1=3Dpassively p=
ulled up
to high if no other is driving low). The outport latch will then be set hig=
h if
you do a bsf/bcf on another bit in the port register (again, not the latch
register) when the tris bit is set to 1 for the bus pin. In this situation =
it
is not enough to change the tris to 0 but you also have to change the port
latch back to 0 before.

/Ruben

=20
> On Fri, 06 Dec 2013 13:00:36 -0700, Dwayne Reid wrote:
> > At 12:06 PM 12/6/2013, Matt Pobursky wrote:
> >> Dwayne,
> >>
> >> Since the output port bit and TRIS latches are separate registers, you
> >> can toggle the TRIS bit all day long and not change the logic level of
> >> the port bit. It will simply toggle the port bit from Hi-z (input) to
> >> output at whatever level is set in the output port bit latch.
> >>
> >> You can only get into trouble with R-M-W when the port is read then
> >> written back to the port bit registers.
> >>
> >
> > You are close to what I am talking about but missed the mark just a bit=
:
> > I set the pin to o/p,
>=20
> write 0 to TRIS register bit -- pin output bit latch unaffected, output p=
in will
> actively drive whatever logic level it was before clearing TRIS bit
>=20
> > write that pin to being LO,
>=20
> write 0 to output latch bit, output will actively drive LOW
>=20
> >then turn the pin back to i/p and *read* a logic HI on the pin
>=20
> write 1 to TRIS register bit, output port bit latch unaffected, output bi=
t
> is still LOW, but output pin is Hi-z so reads whatever logic level is
> present at pin.
>=20
> > Question: what state is the pin output latch in now?
>=20
> Output latch is still 0 as reading the port or setting/clearing the TRIS
> register does not affect the output latch
>=20
> Think about this -- if read port register instructions affected the outpu=
t
> bit latch states then all port reads would result in unpredictable port
> operation.
>=20
> If you look at the block diagram of the PIC IO port structure in any of t=
he data
> sheets, you'll see that the only way an output bit latch is changed is wi=
th a
> write operation.
>=20
> I've done this numerous times where I set the port bit low, set pin to
> output to discharge a capacitor, set pin back to input which allows a the
> cap charge, read and wait for a logic 1 state (RC timing on one pin).
> Alternate discharging and timing by setting or clearing the TRIS bit, nev=
er have
> to change the logic 0 on the port bit latch as it's persistent. I suspect=
 you
> are doing something very similar to this.
>=20
> > My recollection is that the pin is read in the quadrature clock phase Q=
1
> > or Q2 and the pin latch is written in Q3 or Q4.
> >
> > dwayne
>=20
>=20
> --=20
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> View/change your membership options at
> http://mailman.mit.edu/mailman/listinfo/piclist
>=20
>=20
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>=20



=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
Ruben J=F6nsson
AB Liros Electronic
Box 9124
200 39 Malm=F6 Sweden
Tel +46 40142078
ruben@rjjournal.net
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D

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