On Fri, 06 Dec 2013 13:00:36 -0700, Dwayne Reid wrote:
> At 12:06 PM 12/6/2013, Matt Pobursky wrote:
>> Dwayne,
>>
>> Since the output port bit and TRIS latches are separate registers, you
>> can toggle the TRIS bit all day long and not change the logic level of
>> the port bit. It will simply toggle the port bit from Hi-z (input) to
>> output at whatever level is set in the output port bit latch.
>>
>> You can only get into trouble with R-M-W when the port is read then
>> written back to the port bit registers.
>>
>
> You are close to what I am talking about but missed the mark just a bit:
> I set the pin to o/p,

write 0 to TRIS register bit -- pin output bit latch unaffected, output pin
will actively drive whatever logic level it was before clearing TRIS bit

> write that pin to being LO,

write 0 to output latch bit, output will actively drive LOW

>then turn the pin back to i/p and *read* a logic HI on the pin

write 1 to TRIS register bit, output port bit latch unaffected, output bit
is still LOW, but output pin is Hi-z so reads whatever logic level is
present at pin.

> Question: what state is the pin output latch in now?

Output latch is still 0 as reading the port or setting/clearing the TRIS
register does not affect the output latch

Think about this -- if read port register instructions affected the output
bit latch states then all port reads would result in unpredictable port ope=
ration.

If you look at the block diagram of the PIC IO port structure in any of the=
 data
sheets, you'll see that the only way an output bit latch is changed is with
a write operation.

I've done this numerous times where I set the port bit low, set pin to
output to discharge a capacitor, set pin back to input which allows a the
cap charge, read and wait for a logic 1 state (RC timing on one pin).
Alternate discharging and timing by setting or clearing the TRIS bit, never
have to change the logic 0 on the port bit latch as it's persistent. I
suspect you are doing something very similar to this.

> My recollection is that the pin is read in the quadrature clock phase Q1
> or Q2 and the pin latch is written in Q3 or Q4.
>
> dwayne


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