I should add that your bitstream output from the design software also tells the FPGA what content to put in all of the LUTs and how to connect the reset and clock inputs of each functional block's registers to the network of wires. There are always a few special sets of wires which are intended to distribute clock signals with the minimum amount of skew to many registers on the chip at once. These are referred to as primary clock routing resources or splines. On Tue, Oct 8, 2013 at 11:57 AM, Sean Breheny wrote: > Think of an FPGA as an array of functional units which each have a small > lookup table and some registers (flip-flops). On top of this, there are > usually some blocks containing a small amount of fast RAM and a vast > network of "wires" criss-crossing the entire array in a pattern which is > considered efficient for making arbitrary interconnections. Each function= al > block may have, say, four inputs and four outputs as well as reset and > clock lines. The lookup table (LUT) in each can implement any four input, > four output combinational logic function. This can be combined with the > LUTs from other adjacent blocks to make more complex logic functions. For > various reasons, especially to deal with the propagation time required fo= r > a signal to progress through several cascaded LUTs, most designs will use > the registers to store the partial result of a logic function at each clo= ck > edge and then feed this stored data to other LUTs on the next clock edge. > > The functional blocks are, I believe, connected to or disconnected from > routing wires using "transfer gates" which are very similar to analog > switches (FETs which can be ON or OFF to connect or disconnect two circui= t > nodes). The software synthesizer you use to compile your VHDL or Verilog > ultimately generates a bitstream which the FPGA uses to set the state of > all of these transfer gates. This produces a particular interconnection o= f > functional blocks to produce a state machine, which can implement any > combinational and or sequential logic function which can be implemented i= n > a finite state machine, within the size and speed limitations of the FPGA= .. > > > On Tue, Oct 8, 2013 at 10:47 AM, Lindy Mayfield w= rote: > >> Every time someone explains things to me, I get even more questions. Bu= t >> I have to be careful and research myself before asking. >> >> Like, I was going to ask what sorts of "building blocks" an FPGA has, >> because it wasn't clear to me before. I was going to ask, "can I use on= e >> to build a theremin?" >> >> And then I discovered FPAA's. Oh my. :-) >> >> -----Original Message----- >> From: piclist-bounces@mit.edu [mailto:piclist-bounces@mit.edu] On Behalf >> Of RussellMc >> Sent: Tuesday, October 08, 2013 2:50 PM >> To: Microcontroller discussion list - Public. >> Subject: Re: [EE] Hobbyist FPGA development boards? >> >> [EE] would be an approriate tag to discuss FPGA matters under. >> >> >> Russell >> >> >> -- >> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive >> View/change your membership options at >> http://mailman.mit.edu/mailman/listinfo/piclist >> > > --=20 http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .