>> David VanHorn wrote: >> What happens when the fet turns on and the inductance in the source lead >> causes the source voltage to rise faster than the gate voltage is rising= ? > Hummmmm interesting. If the NFET is being used as a low-side switch, > i.e. source is connected to a (good, low-inductance) ground, then this > shouldn't be an issue. For many values of 'shouldn't'. But not all. Driven MOSFETs oscillate parasitically sometimes. How much sense it makes depends on how much you understand reality and how well you get on with Murphy. If it matters, protect against it. A small gate drive resistor is unlikely to cause significant slow down problems in situations that mere mortals will usually encounter. For say 10 Ohm and 1 nF gate capacitance the time constant is 10 ns. In most cases where that matters you will be using an IGBT. If gate capacitance is 10 nF, as it can be, then odds are you are not running it this fast. A gate resistor can take the edge off the as -infinite-as-you-allow-it-to-be gate capacitor inrush currents and may reduce switching losses. (Your driver may be rated at 1A - your initial drive current may be able to be quite a lot higher if driver power rail is well decoupled and driver impedance is not the limiting factor.) A reverse Schottky diode connected g-s AT the FET will clamp negative going gate signals rather severely and a waveform with enough positive voltage to turn on even a very low Vgsth FET will have trouble sustaining itself if its negative half cycles are being clamped to about 0.3V. This is a very time honoured form of MOSFET spurious oscillation protection. A ferrite bead slid onto the drain lead plays havoc with signals that are substantially higher than you are liable to usually be (intending to be) switching with a MOSFET. (I have done this only one 'in anger' long ago on a SMPS). If drain is connected via the device tab rather than the Drain lead then you can look at effect if you slide the bead onto gate or source leads. __________ Related: A reverse biased g-s zener does not address parasitic oscillations but stops Millar capacitance (or anything else) coupling in reactive signals on the Drain (or to the gate from anywhere else) and exposing the amazingly thin gate oxide to drain level voltages. I have had designs which repeatably died within minutes in operation without such a zener and which lived indefinitely with one. Others report similar. This is such an effective protector that I will now always include such a zener as of right in any power MOSFET driver design and THEN decide if there is any good reason to take it out. Such over voltage gate issues can occur even with low impedance gate drivers and small resistance drive resistors. Millar and Murphy working together can be very effective. Related: Zeners that fail under energy dump conditions almost always fail short - but occasionally they fail open just so you cannot safely design around the fail-short assumption. MOSFETS that fail under energy dump (perhaps after an over voltage spike) will perhaps fail short DS mostly but can certainly include the gate a fair amount of the time with D-S-G fused together, and if I ever got D-G only I would not be utterly surprised (probably DSG with S bond wire burned off. (Memory says I had a few of those in a project in about 2000 - 2001 but memory may by now be lying.)(Most were DS). OC is definitely possible with eg bond wire detachment or burnout, but this seems less common. YMMV. O/C fail may give you a nice parting inductive spike depending on circuit and where/what protection is. SO when a FET fails you can assume that HV MAY go anywhere. . Russell McMahon Applied Technology ltd Auckland, New Zealand. --=20 http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .