> My question now is has the main loop finally been restructured to operate > on an event basis. The interrupt has a 1 mS trigger. The ISR keeps a coun= t > of 200 (hopefully finally counting down instead of counting up as the las= t The assignment was as follows. 1. The framework has to be maintained. 2. The interrupt to be 1 mS @ 20 MHz Fosc. 3. Counter to decrement every 100 mS in the interrupt. In the main loop, a state machine was monitoring the counters and=20 toggling the LED. So the on time was to be 200 mS (single register) and off time was to be=20 30 seconds (double register). This looks like an assignment where in all type of issues had to be=20 addressed ( 20 MHz clock, 1 mS interrupt, counter decrement at 100 mS,=20 on time 200 mS and off time 30 seconds). Ravi --=20 http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .