> Note two EUSART errata for Rev A1 of the silicon: the 1/256 chance the RX=
 will miss
> the start bit edge, and the LSB of TX data may be corrupt.
>=20
> Yep, not even kidding, the 1/256 chance error happens depending on how th=
e baud rate
> is generated with BRGH and BRG16.
>=20
> See errata document DS80512F #5.1 and 5.2
>=20
> The RX error errata is the root cause of a > $10K personal loss on a proj=
ect, a
> combination of this crazy problem and an idiot client.
> THANKS MICROCHIP!

Grief ... and how long has the Verilog/VHDL code for UARTS been around work=
ing successfully ???

What do these clowns think they are doing playing with it ?




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