On Tue, 2013-07-09 at 21:08 +0300, Yigit Turgut wrote:
> Thus I am looking for options to choose  a very stable clock source (200M=
Hz
> would be great but I can live with the 100MHz as well). I am sure some of
> you experienced this scheme before and can provide some insight.

What's "very stable"? Without a spec it's kinda hard to recommend
anything.

We usually us an oscillator. For most purposes they have been more then
enough (only time I haven't used an oscillator is when what I'm
connecting the FPGA to has a clock source, in my cases a PCIE slot once
and a video ADC in another).

I am confused why you'd need an externally generated 200MHz clock
source, and why you can only "live" with a 100MHz source? This is an
FPGA. They have TONS of onboard clocking resources available, from PLLs
with integrated deskewing to clock dividers. I say put whatever cheap
oscillator you want on the board and use the FPGA's resources to
generate all the clocks you need. Avoid high speed clocks on your board
as much as possible.

I usually use a 27MHz oscillator since that's what I usually have on
hand and generate internally whatever clock I might require.

TTYL

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