Is it a CMOS 555 timer? The TTL versions can be rather thirsty on the
transitions, o/p is a 200ma sink/source, you didn't quote a pull up
resistor on the o/p. A decoupling cap across the 555 supply is really a
must.


On Wed, May 1, 2013 at 11:10 PM, Spehro Pefhany <speff@interlog.com> wrote:

> At 04:57 PM 5/1/2013, you wrote:
> >I'm feeling quite like an idiot..because this should be
> >obvious...and so simple...its EE101 stuff
> >
> >74HC74 dual D flip flop
> >
> >clear and preset tied high (5V) thru a resistor (10K)
> >
> >D connected to !Q
> >
> >clock driven by a 555 timer as a one shot from an external trigger
> >
> >Q drives into another circuit
> >
> >Customer does NOT want a programmable part....
> >
> >So the 555 generates the active high pulse just fine
> >
> >The D ff doesnt behave.  The Q ouput just follows the length of the
> >clock pulse.    It should toggle states on each rising edge of the
> >555 ouput.  Q out is low,!Q is high, clock comes in....D goes
> >hi...but goes back low when the clock pulse goes away.
> >
> >grrrrrrrr.......
> high)?
>
> Haywired? Or nicely laid out?
>
> Is it a CMOS "555" with proper CMOS logic levels on the output?
>
> Try disconnecting that thing wot it's driving in case you're getting
> ground bounce
> causing a double tap.
>
>
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