At 10:50 PM 01/05/2013, you wrote:


>Note his very last paragraph re required DAC resolution.
>
>Russell: Need for a super DAC may be able to be relaxed if you have a
>lower resolution DAC and can "nudge it up or down a bit" independently
>and use the ADC to control what is happening.
>               Russell

(snippage)

>____________
>
>Note also that 10uA to 1A range mentioned implies a 10uA programming=20
>resolution
>over 5 decades (a resolution of 1 part in 100k)  - which would=20
>require a 17-bit
>resolution DAC.  That would significantly constrain the choice of DAC devi=
ce.

If the requirement is to be able to sink/source a programmed current of
  1A ~10uA +/- 0.01% of setpoint, then the error due to
quantization + circuit error has to be less than +/-1nA at the low end.
Allow 12.5% of that error budget for the quantization error, so we need
bits =3D (1/ln(2))*ln(1A/1nA)+ 3 ~=3D 33 bits to be able to do it in one ra=
nge.

That's just not going to happen under sensible constraints.

Consider the feedback- if it's a 1R resistor, you get 1V at 1A. At 10uA
you get 10uV for the _entire_ signal. If you want to control that to 0.01%
you can afford only a total error of 1nV. <1uV is challenging enough under
normal circumstances. CMRR requirements with a naive implementation using
a Howland topology.. 8-(

Using five decade ranges, the bits required on each range is
bits =3D (1/ln(2))*ln(100/0.01)+ 3 ~=3D 16 bits, which is not a problem- th=
is
is exactly what the commercial instruments do.

--sp



--=20
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