Hi Sean, The setup is quite standard; A dsPIC with PWM1H/L driving an IR2110 as gate driver for a MOSFET push pull stage, driving a ferrite core transforme= r, to which a resistive lamp load of 60W at 230V is connected. The schematic is the same as earlier, no changes: http://farm8.staticflickr.com/7113/8169359354_e5ff2e023a_c_d.jpg http://www.flickr.com/photos/79743192@N07/8169359354/sizes/c/in/photostream= / Just that there are no capacitors across the primary side of the transforme= r. Notes about the transformer: ETD39, N87 material from EPCOS Primary: 2+2 turns of 0.4mm cu wire with 24 strands paralleled together Secondary: 68 turns of 0.4mm cu wire, single strand. Primary1 is wound first, Secondary is wound just above Primary1. Primary2 is wound on top of the Secondary. Each winding is insulated with polyester tape. Core is ungapped. Transformer is designed for 160W, with a flux change of 500 Gauss (Core is capable of handling about 2000 Gauss, but for safety sake, the flu= x change is kept so ridiculously small in comparison), running at 12VDC, Output rated at 325VDC. Frequency of operation is 100kHz (square wave) There is no feedback as of now: (current mode, voltage mode ..) Current duty cycle is 32% on each limb, 64% total, in all. There is only negligible temperature rise with the transformer, about 3-4 degrees likely. The MOSFET, on one of the limbs (the one connected to the transformer innermost primary winding) do get really hot after about some 20 seconds of operation with the lamp load and keep on increasing (the heating up doesn't cause the Rds ON to increase and thus lower current. I just switch it off at about a minute and by this time, the heatsink is really too hot to touch). Regards, Manu On Thu, Apr 18, 2013 at 9:47 AM, Sean Breheny wrote: > Hi Manu, > > Is there some way I could see a schematic of your set-up? If the > half-bridge is on one side of the transformer primary, what is the other > end of the primary connected to? > > I looked back through my notes and my project used a full-bridge converte= r > with a duty cycle which was constant. I was able to avoid flux walking by > just keeping the duty cycle very close to 50% and then leaving some > dead-time in the cycle which allowed diode conduction to ramp any remaini= ng > current to zero. This was aided by the winding resistance. > > Sean > > > > On Wed, Apr 17, 2013 at 6:31 PM, Manu Abraham wro= te: > >> Hi Sean, >> >> On Thu, Apr 18, 2013 at 3:27 AM, Sean Breheny wrote: >> > Hi Manu, >> > >> > I am not familiar with the PWM peripheral on the pic you are using but >> > usually cycle-by-cycle current limiting means very simply this: >> constantly >> > checking to see if the current is outside of some window (say, for >> example, >> > +/- 10 Amps) and when it goes outside this window, terminate the >> remainder >> > of the present PWM cycle (i.e., turn off all FETs and let the current = go >> > through the body diodes back into the bus) and then recheck the curren= t >> at >> > the beginning of the next PWM cycle. If it is now inside the window, >> > re-enable PWM as normal. If not, keep the FETs off for another whole P= WM >> > cycle and check the current again at the beginning of the next PWM cyc= le, >> > etc. >> > >> > "cycle-by-cycle" meaning that the exit from current limit is synchrono= us >> > with the beginning of a new cycle, to avoid increasing switching losse= s >> by >> > allowing the system to introduce additional on/off edges beyond what >> would >> > happen in normal PWM. >> > >> > I don't think this is what you want to prevent flux walking because, i= f >> you >> > used such a scheme, and the current tended to increase in one particul= ar >> > direction, then it would just keep hitting current limit in that >> direction. >> > You want some scheme which prevents the average flux from growing beyo= nd >> > some tiny value in the first place, and this value would be much less >> than >> > the peak flux achieved during each ON cycle. >> > >> > I've worked this out before in an SMPS design and I think, if I rememb= er >> > correctly, that I got around it by simply increasing the PWM dead-time >> > (time from turning off one set of FETs, or in your case, one FET, to >> > turning on the next FETs) a little bit so that the current would alway= s >> > decay to zero within each half PWM cycle. I'll have to look back at my >> > notes again. >> >> This was what I was thinking. I did simply play with the Dead time a bit >> here and there. It did help to some extend, but it still didn't fix the >> problem >> as expected. >> >> In short, there are 2 problems that were occurring, quite inversely: >> >> #1, Flux walking problem: this reduced a bit by increasing dead time >> #2, As pulse width reduced, current increased per pulse, causing >> switching loss again. >> >> It looked like a bit too hard to reach the in-between stage empirically. >> >> It would be great, if you could have a look at your notes again, >> >> Thanks, >> >> Manu >> -- >> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive >> View/change your membership options at >> http://mailman.mit.edu/mailman/listinfo/piclist >> > -- > http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive > View/change your membership options at > http://mailman.mit.edu/mailman/listinfo/piclist --=20 http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .