Hi Manu,

Is there some way I could see a schematic of your set-up? If the
half-bridge is on one side of the transformer primary, what is the other
end of the primary connected to?

I looked back through my notes and my project used a full-bridge converter
with a duty cycle which was constant. I was able to avoid flux walking by
just keeping the duty cycle very close to 50% and then leaving some
dead-time in the cycle which allowed diode conduction to ramp any remaining
current to zero. This was aided by the winding resistance.

Sean



On Wed, Apr 17, 2013 at 6:31 PM, Manu Abraham <abraham.manu@gmail.com>wrote=
:

> Hi Sean,
>
> On Thu, Apr 18, 2013 at 3:27 AM, Sean Breheny <shb7@cornell.edu> wrote:
> > Hi Manu,
> >
> > I am not familiar with the PWM peripheral on the pic you are using but
> > usually cycle-by-cycle current limiting means very simply this:
> constantly
> > checking to see if the current is outside of some window (say, for
> example,
> > +/- 10 Amps) and when it goes outside this window, terminate the
> remainder
> > of the present PWM cycle (i.e., turn off all FETs and let the current g=
o
> > through the body diodes back into the bus) and then recheck the current
> at
> > the beginning of the next PWM cycle. If it is now inside the window,
> > re-enable PWM as normal. If not, keep the FETs off for another whole PW=
M
> > cycle and check the current again at the beginning of the next PWM cycl=
e,
> > etc.
> >
> > "cycle-by-cycle" meaning that the exit from current limit is synchronou=
s
> > with the beginning of a new cycle, to avoid increasing switching losses
> by
> > allowing the system to introduce additional on/off edges beyond what
> would
> > happen in normal PWM.
> >
> > I don't think this is what you want to prevent flux walking because, if
> you
> > used such a scheme, and the current tended to increase in one particula=
r
> > direction, then it would just keep hitting current limit in that
> direction.
> > You want some scheme which prevents the average flux from growing beyon=
d
> > some tiny value in the first place, and this value would be much less
> than
> > the peak flux achieved during each ON cycle.
> >
> > I've worked this out before in an SMPS design and I think, if I remembe=
r
> > correctly, that I got around it by simply increasing the PWM dead-time
> > (time from turning off one set of FETs, or in your case, one FET, to
> > turning on the next FETs) a little bit so that the current would always
> > decay to zero within each half PWM cycle. I'll have to look back at my
> > notes again.
>
> This was what I was thinking. I did simply play with the Dead time a bit
> here and there. It did help to some extend, but it still didn't fix the
> problem
> as expected.
>
> In short, there are 2 problems that were occurring, quite inversely:
>
> #1, Flux walking problem: this reduced a bit by increasing dead time
> #2, As pulse width reduced, current increased per pulse, causing
> switching loss again.
>
> It looked like a bit too hard to reach the in-between stage empirically.
>
> It would be great, if you could have a look at your notes again,
>
> Thanks,
>
> Manu
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