Hi Joe, On Thu, Apr 18, 2013 at 3:39 AM, IVP wrote: >> Now limiting applied, PWM is reset, but the transformer core >> might not be reset ?) > > Manu, I looked at this a little bit when designing motor (BLDC > and stepper) drivers using FETs and found it wasn't too much of > an issue. As BAJ mentioned, comparators are included in most, > if not all, driver ICs to monitor winding current > > Joe > > ---------- > > Discussion of BJT (can be problematic) vs FET (generally not) > > http://www.edaboard.com/thread138849.html > > http://www.ti.com/lit/ml/slup126/slup126.pdf > > "In a push-pull converter (bridge, half-bridge, PPCT) duty > cycle D can approach 100% at the switching frequency > (always think of D at the switching frequency, not the > transformer frequency). However, it may be necessary to > limit D to less than 90% to allow a current transformer to > self-reset. > > Often the control IC limits the duty cycle for several reasons > including allowing time for delays in turning off the switch" The maximum duty cycle that I am using per limb is 45%, thus totally 90% as a maximum. But with the transformer calculations, the Duty cycle minimum and nominal values that I get are around 30 - 39% per limb, thus 60 - 78% total. I thought about increasing the gap between the cores, but then that would increasing the magnetising current (which eventually increases conduction losses). This was the reason why I was looking into Cycle-by-Cycle limiting. I eventually followed from BAJ that the limiting is achieved with the Analog comparator, contrary to what was going through my mind (using the ADC, which wouldn't be that fast, probably) Regards, Manu --=20 http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .