On Thu, Apr 18, 2013 at 02:42:22AM +0530, Manu Abraham wrote:
> On Thu, Apr 18, 2013 at 2:42 AM, Byron Jeff <byronjeff@mail.clayton.edu> =
wrote:
> > On Wed, Apr 17, 2013 at 11:56:37PM +0530, Manu Abraham wrote:
> >> Hi,
> >>
> >> As the subject states, how to implement cycle by cycle current limitin=
g
> >> on the dsPIC33F ? (I have been eyeballing DS70323B High Speed PWM,
> >> for quite a while and unable to get a grasp on how it is supposed to w=
ork)
> >>
> >> I understand that one reads in the current through the MOSFET's, but I
> >> am not seeing any ADC related stuff working as described in the doc.
> >> (Maybe, I am missing something here ?)
> >>
> >> Can someone explain the basic idea ?
> >
> > Sure. Current Limiting is a fault. Faults are covered in section 43.10 =
of
> > the document you listed. Each PWM can have faults from selectable sourc=
es.
> >
> > The analog part of it is using a comparator. See section 43.10.1 and
> > Example 43.19 to see how it is done. You take the voltage that matches
> > your current limit and put it on one input of a comparator. You take th=
e
> > voltage that measures your current (using a shunt resistor and possibly=
 an
> > opamp or instrumentation amp to scale) on the other side of the compara=
tor.
> > Then the shunt/amp voltage exceeds the current limit voltage, the
> > comparator changes state, causing a fault. So for example if you had a
> > 10A/100mV shunt and a 10x opamp, the shunt would produce 0.5V at 5A. So=
 if
> > you wanted the current limit to be 5A, you'd put a fixed 0.5V on on
> > comparaitor terminal and the scaled voltage across the shunt to the oth=
er.
> > As long as the current is less than 5A then the scaled voltage across t=
he
> > shunt would be below 0.5V. Once it gets above that, the comparitor chan=
ges
> > state, indicating an overcurrent fault.
> >
> > In 43.10.2.1 FAULT INPUT PIN MODES setting Cycle-by-Cycle mode will cau=
se
> > the PWM to terminate early if a fault is detected. PWM restarts normall=
y at
> > the next cycle. So you get full PWM as long as the current limit is not
> > exceeded. But once the current is exceeded, then the PWM cycle is
> > terminated. Presumably this will cause the current to drop.
>=20
> Thanks for the explanation. The part that kept me confused was that, by
> cycle-by-cycle current limiting, the picture in my head was that, the cur=
rent
> is controlled in each cycle by controlling the duty cycle. The analog
> comparator,
> didn't come into mind at all.
>=20
> The reason that prompted me to think about cycle-by-cycle limiting was to
> get around flux walking in a push pull configuration. But if I am killing=
 off a
> pulse and restarting the PWM, does cycle-by-cycle limiting help ? (ie PWM=
H
> goes active, goes inactive PWML goes active, flux starts to walk on eithe=
r
> PWMH or L. Now limiting applied, PWM is reset, but the transformer core
> might not be reset ?)
>=20
> Does the limiting help in such a case, to avoid flux walking ?
>=20
> Thanks,
>=20
> Manu
> --=20
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This is above my pay grade. Here's a thread on the subject that seems to be
relevant:

http://www.edaboard.com/thread138849.html

--=20
Byron A. Jeff
Chair: Department of Computer Science and Information Technology
College of Information and Mathematical Sciences
Clayton State University
http://faculty.clayton.edu/bjeff
--=20
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