Hi Manu, I am not familiar with the PWM peripheral on the pic you are using but usually cycle-by-cycle current limiting means very simply this: constantly checking to see if the current is outside of some window (say, for example, +/- 10 Amps) and when it goes outside this window, terminate the remainder of the present PWM cycle (i.e., turn off all FETs and let the current go through the body diodes back into the bus) and then recheck the current at the beginning of the next PWM cycle. If it is now inside the window, re-enable PWM as normal. If not, keep the FETs off for another whole PWM cycle and check the current again at the beginning of the next PWM cycle, etc. "cycle-by-cycle" meaning that the exit from current limit is synchronous with the beginning of a new cycle, to avoid increasing switching losses by allowing the system to introduce additional on/off edges beyond what would happen in normal PWM. I don't think this is what you want to prevent flux walking because, if you used such a scheme, and the current tended to increase in one particular direction, then it would just keep hitting current limit in that direction. You want some scheme which prevents the average flux from growing beyond some tiny value in the first place, and this value would be much less than the peak flux achieved during each ON cycle. I've worked this out before in an SMPS design and I think, if I remember correctly, that I got around it by simply increasing the PWM dead-time (time from turning off one set of FETs, or in your case, one FET, to turning on the next FETs) a little bit so that the current would always decay to zero within each half PWM cycle. I'll have to look back at my notes again. Sean On Wed, Apr 17, 2013 at 5:12 PM, Manu Abraham wrote= : > On Thu, Apr 18, 2013 at 2:42 AM, Byron Jeff > wrote: > > On Wed, Apr 17, 2013 at 11:56:37PM +0530, Manu Abraham wrote: > >> Hi, > >> > >> As the subject states, how to implement cycle by cycle current limitin= g > >> on the dsPIC33F ? (I have been eyeballing DS70323B High Speed PWM, > >> for quite a while and unable to get a grasp on how it is supposed to > work) > >> > >> I understand that one reads in the current through the MOSFET's, but I > >> am not seeing any ADC related stuff working as described in the doc. > >> (Maybe, I am missing something here ?) > >> > >> Can someone explain the basic idea ? > > > > Sure. Current Limiting is a fault. Faults are covered in section 43.10 = of > > the document you listed. Each PWM can have faults from selectable > sources. > > > > The analog part of it is using a comparator. See section 43.10.1 and > > Example 43.19 to see how it is done. You take the voltage that matches > > your current limit and put it on one input of a comparator. You take th= e > > voltage that measures your current (using a shunt resistor and possibly > an > > opamp or instrumentation amp to scale) on the other side of the > comparator. > > Then the shunt/amp voltage exceeds the current limit voltage, the > > comparator changes state, causing a fault. So for example if you had a > > 10A/100mV shunt and a 10x opamp, the shunt would produce 0.5V at 5A. So > if > > you wanted the current limit to be 5A, you'd put a fixed 0.5V on on > > comparaitor terminal and the scaled voltage across the shunt to the > other. > > As long as the current is less than 5A then the scaled voltage across t= he > > shunt would be below 0.5V. Once it gets above that, the comparitor > changes > > state, indicating an overcurrent fault. > > > > In 43.10.2.1 FAULT INPUT PIN MODES setting Cycle-by-Cycle mode will cau= se > > the PWM to terminate early if a fault is detected. PWM restarts normall= y > at > > the next cycle. So you get full PWM as long as the current limit is not > > exceeded. But once the current is exceeded, then the PWM cycle is > > terminated. Presumably this will cause the current to drop. > > Thanks for the explanation. The part that kept me confused was that, by > cycle-by-cycle current limiting, the picture in my head was that, the > current > is controlled in each cycle by controlling the duty cycle. The analog > comparator, > didn't come into mind at all. > > The reason that prompted me to think about cycle-by-cycle limiting was to > get around flux walking in a push pull configuration. But if I am killing > off a > pulse and restarting the PWM, does cycle-by-cycle limiting help ? (ie PWM= H > goes active, goes inactive PWML goes active, flux starts to walk on eithe= r > PWMH or L. Now limiting applied, PWM is reset, but the transformer core > might not be reset ?) > > Does the limiting help in such a case, to avoid flux walking ? > > Thanks, > > Manu > -- > http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive > View/change your membership options at > http://mailman.mit.edu/mailman/listinfo/piclist > --=20 http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .