>=20
>  >> Yup, that was my plan, I am just worries I will typo something and=20
> suddenly have two parts that don't meet up on the board.
>=20
> > That is what the ERC check is to help with.  It is good at unconnected =
nets and if you also use net classes, catching errors like a signal pin con=
nected to a power net.
> > Rob 		 	   	=09
>=20
> That won't help if you have a certain net name and misspelled it twice=20
> ... Somehow murphy wil triumph!
>=20
/* Olin voice on */
That is not the problem I was describing ERC is designed to detect.
/* Olin voice off */  ;-)
On the whole, you just have to be careful and diligent in your checking of =
things.  Picking a consistent naming convention for signals is a good first=
 step.  After that, get into the habit of naming nets right away if you thi=
nk they will be used anywhere but within an inch or two of their originatin=
g schematic element.  Use the net classes to describe signals too.  Often t=
imes I will label signals even though they don't travel all over creation j=
ust because it helps me keep things clear in my mind and later on the layou=
t.
And many of the libraries freely available for use in Eagle are pretty crum=
my.  They mix and match the use of pin types, have funny labeling schemes, =
inconsistent use of pad sizes, drills, fonts and any number of oddities.  S=
o, be careful with any library you haven't personally written or at the ver=
y least, explored "under the hood".  Free is too frequently worth what you =
paid (and often times less).
Rob 		 	   		 =20
--=20
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