I'm not Mario :-). Bleed resistor is notionally vaguely correct but impractical and unnecessarily high - any leakage at PIC pin will kill the system by eating the 10 or so Nanoamps that you make available to it. Main issue is, if you have a high startup current then Vout may climb too high before loop starts. If Rbleed =3D 10M,Vin max =3D 8V. IRbleed ~=3D (8-0.6)/10M =3D 1 uA say. I NPN =3D~~~ 100 uA. I_PNP boot ~~~=3D 10 mA. Cout and load on Vout will limit rise time. Using Cout for rise time limiting and 3V as max allowed uncontrolled rise, you'll get ABOUT 3 ms/ uF of Cout. So 10 uF =3D 30 mS. 100 uF =3D 300 mS. A safish solution is to add a NPN clamp to the NPN base such that if Vout rises above V_too_high then it turns on clamp and turns off main NPN. You then have a smps in its own right. You can set trip level with a zener or resistor divider to somewhat above the uP will control it at. Hey - we just rererere-invented 'my' GSR switching regulator :-) Mario's system uses (it seems) very high Vin (hundreds of Volts).. You do not say what Vout is but I assume 3V3. With 4 cells your Vin_min is say 4V, not 5V. Vmin for Alkaline, NiCd, NimH is all about 1 V/cell. NPN need not be high current. PNP needs to match your Iout need. You can use lower Beta if desired. I've found BC337.BC327 =3D BC807/BC817 =3D about as cheap as any and better spec than most for glue use. You may want to use lower resistor values in drive to transistors tp get better switching speeds. You may find a speedup cap (start with 0.001 uF) across base drive R's improves waveforms. Russell On 23 February 2013 13:27, Veronica Merryfield wrote: > Dear Mario > > I wonder if I could cross check my numbers with you. It has taken me a wh= ir to get back to doing this mainly because when I was initially asking it = was just an idea and now it is to be designed. > > So this is a buck regulator running from a 4 cell battery pack, so I am a= ssuming I have a min voltage of 5v. When the unit is on charger, the input = will be nearer 7 to 8 volts. > > My PNP is 500mA max, hfs of 100 min. The NPNP is 600mA with a min hfs of = 100. These choices were cost driven within the required specs. > > I get a PNP base resistor of about 700 ohms, NPN base resistor of 10K (lo= wer than the limit) and a bleed resistor of 380M to give me a bootstrap cur= rent of 100uA for a 31Khz LF-INT PIC oscillator. I could up the boot strap = to current to 700uA and start with a 1Mhz HF-INT osc. > > When I got 380M I became doubtful of my figures and wanted to cross check= with you. > > Thanks > > Veronica > > > On 2012-06-11, at 11:28 PM, Electron wrote: > >> >> Dear Veronica, >> >> >> At 01.33 2012.06.12, you wrote: >>> Hi all >>> >>> Has anyone worked on a system using PWM to create a SMPSU where the >>> PIC/MCU supply is being generated from the PWM. I know this will need >>> a bootstrap mechanism and I guess that is what I am most interested. >> >> Yes, in my buck controller the PNP switch is driven by a NPN transistor, >> whose base is pulled up. The Vreg of the MPU is after this PNP high swit= ch. >> >> When power arrives, the PNP high side switch is not fully saturated but >> lets nice electrons pass, thanks to the pullup on the NPN transistor tha= t >> drives the PNP base, and power leaks into the VReg and consequently the = MPU, >> which is held in reset until power is good ( =3D voltage at VReg is with= in >> 98% or so of stable output voltage). >> >> At this point the reset line is not held down anymore, the MPU gets out = of >> reset, and drives the NPN transistor base actively, 0 or 1, not tristate >> anymore, being thus able to saturate the PNP transistor or switch it off >> completely. >> >> It works, and the oscilloscope shows that it even works very well. >> >> I can give more details if you want, e.g. it's even a high tension power >> input (400V). NPN collector into PNP base (through a resistor of course)= , >> NPN base pulled up via high value resistor to PNP emitter. Not exactly, >> as the pullup resistor doesn't go into NPN base but into MPU pin, and >> the latter goes, through a low value resistor, into NPN base. The MPU pi= n >> never seen high voltage, as it's clamped by the NPN base, through the lo= w >> value resistor. Currents into base, out of pin, etc.. are all much withi= n >> absolute max values, always, when MPU I/O pin is tristated, as well as w= hen >> it is actively driven to 0 or 1. >> >> One difference with your design is that I don't use PWM, but I drive the >> NPN base directly via an algorithm (my MPU is doing much more than the >> buck part, it's a complex/articulated system), but it doesn't change the >> substance, as after reset you can enable the PWM module instead of bit >> banging the I/O pin like I do. >> >> >>> Thanks >> >> I'm really very glad if I had a chance to help you. >> >> Cheers, >> Mario >> >> >>> >>> Veronica >>> >>> >>> -- >>> http://www.piclist.com PIC/SX FAQ & list archive >>> View/change your membership options at >>> http://mailman.mit.edu/mailman/listinfo/piclist >> >> -- >> http://www.piclist.com PIC/SX FAQ & list archive >> View/change your membership options at >> http://mailman.mit.edu/mailman/listinfo/piclist > > > -- > http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive > View/change your membership options at > http://mailman.mit.edu/mailman/listinfo/piclist --=20 http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .