There will always be some jitter due to the sampling clock of the logic analyzer not being synchronous to the PIC's clock. The magnitude peak-to-peak of this jitter should be about twice the logic analyzer's sampling interval.So, at 10MHz sampling, you would expect +/- 100ns jitter. On a 3MHz signal, that would show up as a frequency which varies from 2.3MHz (433ns period) to 4.3MHz (233ns period). Are you sure that the logic analyzer can sample reliably at 200MHz? I tried to look it up and it seems to say "70+MHz sampling". If you really are sampling at 200MHz, I would expect +/-5ns jitter. On the same 3MHz signal, this would show up as a frequency variation from 2.96MHz to 3.05MHz. Note that it is still possible to measure the frequency accurately by averaging over many cycles, but the logic analyzer will fundamentally be unable to see whether there is jitter in the original actual signal below the magnitude of the jitter due to its own sampling interval. I don't understand what you mean about oscillator switching or Primary PLL affecting the jitter. If those features are in the PIC, turning them on or off should not affect the way that the logic analyzer causes jitter. If enabling or disabling a feature on the PIC drastically reduces the jitter, then I would suspect that something is indeed wrong with the PIC circuit. You may also want to make sure that interrupts are disabled on your PIC to avoid jitter due to interrupts happening in the middle of your while(1) loop. In addition, I would look at the generated assembly code to make sure that the loop is getting coded in a way which should in fact result in zero jitter. Sean On Tue, Feb 19, 2013 at 6:30 PM, Manu Abraham wrot= e: > Hi Sean, > > Using an Open Logic Sniffer at my side. > > I guess you are right. As the sampling rate was increased, the oddity > reduced but still pertains to some extend. Initially, I was using about > 10MHz sampling rate, eventually 200Mhz. > > While I disabled Clock switching/Primary PLL, the jitter almost vanished > which was pointing to some kind of aliasing issue with the Logic Sniffer= , > but was a bit harder to confirm. > > Thanks, > Manu > > > On Wed, Feb 20, 2013 at 4:47 AM, Sean Breheny wrote: >> Hi Manu, >> >> What kind of logic analyzer are you using? I assume that you have it >> set to "timing" acquisition mode where it simply takes samples at a >> fixed rate. Do you know what that rate is? Maybe it is too slow to >> capture the full speed signal and you are getting aliasing that makes >> it look like the frequency is jittering. While aliasing with sine >> waves and high-resolution sampling does not produce a variable >> frequency output, 1-bit sampling can indeed result in a repetitive >> pattern which does not have a simple square-wave pattern. >> >> Sean >> >> >> On Tue, Feb 19, 2013 at 11:00 AM, Manu Abraham = wrote: >>> Hi, >>> >>> I have a dsPIC33FJ16GS502 with a 10MHz xtal as the Primary Oscillator, >>> connected between OSC1 and OSC2 along with 2x15pf caps. >>> >>> While expecting the device to run at 40MIPS, all I see is that RA3 >>> toggles around 3.3Mhz and 5MHz as can be seen. >>> >>> RA3 is connected to a LED and Channel 1 of a Logic Sniffer.. >>> >>> http://farm9.staticflickr.com/8515/8489682002_9fcb64b961_b_d.jpg >>> >>> Any idea why this "jitter" ? Any pointers would be helpful. >>> >>> The code that toggles RA3 is as follows: >>> >>> #include >>> #include >>> >>> >>> _FOSCSEL(FNOSC_PRI) /* Primary Osc (XT, HS, EC) */ >>> _FOSC(POSCMD_XT & OSCIOFNC_OFF & FCKSM_CSECMD) /* XT Osc, OSCO pin >>> is CLK out, sw ena, mod disabled */ >>> _FWDT(FWDTEN_OFF) /* Watchdog Timer disabled */ >>> _FPOR(FPWRT_PWR128 & BOREN_OFF) /* POR Timer 128mS, Brown-out Reset >>> disabled */ >>> _FICD(ICS_PGD3 & JTAGEN_OFF) /* Use PGC3/EMUC3 and PGD3/EMUD3, JTAG >>> Port disabled */ >>> >>> >>> void setup_xtosc(void) >>> { >>> /* Configure PLL prescaler, PLL postscaler, PLL divisor */ >>> PLLFBD =3D 32; >>> CLKDIVbits.PLLPOST =3D 0; /* N1 =3D 2 */ >>> CLKDIVbits.PLLPRE =3D 0; /* N2 =3D 2 */ >>> >>> __builtin_write_OSCCONH(0x03); /* switch to Pri. Osc+PLL (NOSC= =3D0b011) */ >>> __builtin_write_OSCCONL(0x01); /* enable switch */ >>> >>> while (OSCCONbits.COSC !=3D 0x03); /* wait for clock to switch */ >>> while (OSCCONbits.LOCK !=3D 0x01); /* wait for PLL to lock */ >>> >>> } >>> >>> int main(void) >>> { >>> setup_xtosc(); >>> TRISA =3D 0; >>> >>> while (1) { >>> __builtin_btg((unsigned int *)&LATA, 3); /* toggle RA3 */ >>> Nop(); >>> } >>> return 0; >>> } >>> >>> >>> Thanks, >>> Manu >>> -- >>> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive >>> View/change your membership options at >>> http://mailman.mit.edu/mailman/listinfo/piclist >> -- >> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive >> View/change your membership options at >> http://mailman.mit.edu/mailman/listinfo/piclist > -- > http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive > View/change your membership options at > http://mailman.mit.edu/mailman/listinfo/piclist --=20 http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .