Hi,

According to the datasheet:
http://ww1.microchip.com/downloads/en/DeviceDoc/70318F.pdf

The primary oscillator can use one of the following as
its clock source:
=95 XT (Crystal): Crystals and ceramic resonators in
the range of 3 MHz to 10 MHz. The crystal is
connected to the OSC1 and OSC2 pins.

=95 HS (High-Speed Crystal): Crystals in the range of
10 MHz to 40 MHz. The crystal is connected to
the OSC1 and OSC2 pins.


It doesn't make any difference if I use XT or HS.

Regards,

Manu


On Tue, Feb 19, 2013 at 9:51 PM, Jan-Erik Soderholm
<jan-erik.soderholm@telia.com> wrote:
> Hi.
>
>  > _FOSC(POSCMD_XT & OSCIOFNC_OFF & FCKSM_CSECMD)    /* XT Osc, OSCO pin
>
> Not sure that it matters, but doesn't a 10 MHz xtal
> qualify as an "HS" xtal ? I doesn't even know if there
> are separate XT/HS settings on that processor... :-)
>
> Jan-Erik.
>
>
>
> Manu Abraham wrote 2013-02-19 17:00:
>> Hi,
>>
>> I have a dsPIC33FJ16GS502 with a 10MHz xtal as the Primary Oscillator,
>> connected between OSC1 and OSC2 along with 2x15pf caps.
>>
>> While expecting the device to run at 40MIPS, all I see is that RA3
>> toggles around 3.3Mhz and 5MHz as can be seen.
>>
>> RA3 is connected to a LED and Channel 1 of a Logic Sniffer..
>>
>> http://farm9.staticflickr.com/8515/8489682002_9fcb64b961_b_d.jpg
>>
>> Any idea why this "jitter" ? Any pointers would be helpful.
>>
>> The code that toggles RA3 is as follows:
>>
>> #include <p33fj16gs502.h>
>> #include <libpic30.h>
>>
>>
>> _FOSCSEL(FNOSC_PRI)    /* Primary Osc (XT, HS, EC) */
>> _FOSC(POSCMD_XT & OSCIOFNC_OFF & FCKSM_CSECMD)    /* XT Osc, OSCO pin
>> is CLK out, sw ena, mod disabled */
>> _FWDT(FWDTEN_OFF)    /* Watchdog Timer disabled */
>> _FPOR(FPWRT_PWR128 & BOREN_OFF)    /* POR Timer 128mS, Brown-out Reset
>> disabled */
>> _FICD(ICS_PGD3 & JTAGEN_OFF)    /* Use PGC3/EMUC3 and PGD3/EMUD3, JTAG
>> Port disabled */
>>
>>
>> void setup_xtosc(void)
>> {
>>      /* Configure PLL prescaler, PLL postscaler, PLL divisor */
>>      PLLFBD =3D 32;
>>      CLKDIVbits.PLLPOST =3D 0;    /* N1 =3D 2 */
>>      CLKDIVbits.PLLPRE =3D 0;    /* N2 =3D 2 */
>>
>>      __builtin_write_OSCCONH(0x03);    /* switch to Pri. Osc+PLL (NOSC=
=3D0b011) */
>>      __builtin_write_OSCCONL(0x01);    /* enable switch */
>>
>>      while (OSCCONbits.COSC !=3D 0x03); /* wait for clock to switch */
>>      while (OSCCONbits.LOCK !=3D 0x01); /* wait for PLL to lock */
>>
>> }
>>
>> int main(void)
>> {
>>      setup_xtosc();
>>      TRISA =3D 0;
>>
>>      while (1) {
>>          __builtin_btg((unsigned int *)&LATA, 3); /* toggle RA3 */
>>          Nop();
>>      }
>>      return 0;
>> }
>>
>>
>> Thanks,
>> Manu
>>
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